Fuja, Tom and Heegard, Chris and Goodman, Rod (1988) Linear sum codes for random access memories. IEEE Transactions on Computers, 37 (9). pp. 1030-1042. ISSN 0018-9340. doi:10.1109/12.2254. https://resolver.caltech.edu/CaltechAUTHORS:20190314-130609423
![[img]](https://authors.library.caltech.edu/style/images/fileicons/application_pdf.png) |
PDF
- Published Version
See Usage Policy. 1MB |
Use this Persistent URL to link to this item: https://resolver.caltech.edu/CaltechAUTHORS:20190314-130609423
Abstract
Linear sum codes (LSCs) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories (RAMs). They use the natural addressing scheme found on RAMs to form and access codewords with a minimum of overhead. The authors formally define linear sum codes and examine some of their characteristics. Specifically, they examine their minimum distance characteristics, their error correcting capabilities, and the complexity involved in their implementation. In addition, detailed consideration is given to an easily implemented class of single-, double-, and triple-error correcting LSCs.
| Item Type: | Article | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Related URLs: |
| ||||||||||||||||||
| Additional Information: | © 1988 IEEE. Manuscript received May 14, 1986; revised March 30, 1987 and August 14, 1987. This work was supported by NATO Grant 215/84, NSF Grant ECS-8352220, by a grant from AT&T Information Systems, by the AT&T Bell Laboratories Ph.D. Scholarship Program, and by Caltech’s Program in Advanced Technologies sponsored by Aerojet General, General Motors, GTE, and TRW. This work was presented in part at the International Symposium on Information Theory, Brighton, England, June 23-28, 1985, and at the Allerton Conference on Communications, Control, and Computing, The University of Illinois, October 2-4, 1985. | ||||||||||||||||||
| Funders: |
| ||||||||||||||||||
| Subject Keywords: | Error control codes, memory fault tolerance, random access memories, redundancy in RAM’s, semiconductor memories | ||||||||||||||||||
| Issue or Number: | 9 | ||||||||||||||||||
| DOI: | 10.1109/12.2254 | ||||||||||||||||||
| Record Number: | CaltechAUTHORS:20190314-130609423 | ||||||||||||||||||
| Persistent URL: | https://resolver.caltech.edu/CaltechAUTHORS:20190314-130609423 | ||||||||||||||||||
| Official Citation: | T. Fuja, C. Heegard and R. Goodman, "Linear sum codes for random access memories," in IEEE Transactions on Computers, vol. 37, no. 9, pp. 1030-1042, Sept. 1988. doi: 10.1109/12.2254 | ||||||||||||||||||
| Usage Policy: | No commercial reproduction, distribution, display or performance rights in this work are provided. | ||||||||||||||||||
| ID Code: | 93820 | ||||||||||||||||||
| Collection: | CaltechAUTHORS | ||||||||||||||||||
| Deposited By: | George Porter | ||||||||||||||||||
| Deposited On: | 14 Mar 2019 21:11 | ||||||||||||||||||
| Last Modified: | 16 Nov 2021 17:00 |
Repository Staff Only: item control page
