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An efficient asynchronous multiplier

Goodman, Rodney M. and McAuley, Anthony J. (1988) An efficient asynchronous multiplier. In: Proceedings. International Conference on Systolic Arrays. IEEE , Piscataway, NJ, pp. 593-599. ISBN 0818688602.

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An efficient asynchronous serial-parallel multiplier architecture is presented. If offers significant advantages over conventional clocked versions, without some of the drawbacks normally associated with similar asynchronous techniques, such as excessive area. It is shown how a general asynchronous communication element can be designed and illustrated with the CMOS multiplier chip implementation. It is also shown how the multiplier could form the basis for a faster and more robust implementation of the Rivest-Sharmir-Adleman (RSA) public-key cryptosystem.

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Additional Information:© 1988 IEEE.
Record Number:CaltechAUTHORS:20190314-130609515
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Official Citation:R. M. Goodman and A. J. McAuley, "An efficient asynchronous multiplier," [1988] Proceedings. International Conference on Systolic Arrays, San Diego, CA, USA, 1988, pp. 593-599. doi: 10.1109/ARRAYS.1988.18096
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:93821
Deposited By: George Porter
Deposited On:14 Mar 2019 21:12
Last Modified:16 Nov 2021 17:00

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