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A static RAM chip with on-chip error correction

Chiueh, Tzi-Dar and Goodman, Rodney M. and Sayano, Masahiro (1990) A static RAM chip with on-chip error correction. IEEE Journal of Solid-State Circuits, 25 (5). pp. 1290-1294. ISSN 0018-9200. https://resolver.caltech.edu/CaltechAUTHORS:20190314-142000592

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Abstract

This paper describes a 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip). The chip employs the linear sum code (LSC) technique to perform error detection and correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with 3-µm feature size. Testing results of the actual chip shows a significant improvement in random error tolerance.


Item Type:Article
Related URLs:
URLURL TypeDescription
https://doi.org/10.1109/4.62154DOIArticle
Additional Information:© 1990 IEEE. Manuscript received August 11, 1989; revised February 26, 1990. This work was supported in part by NSF Grant MIP-8711568.
Funders:
Funding AgencyGrant Number
NSFMIP-8711568
Issue or Number:5
Record Number:CaltechAUTHORS:20190314-142000592
Persistent URL:https://resolver.caltech.edu/CaltechAUTHORS:20190314-142000592
Official Citation:T. -. Chiueh, R. M. Goodman and M. Sayano, "A static RAM chip with on-chip error correction," in IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1290-1294, Oct. 1990. doi: 10.1109/4.62154
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:93834
Collection:CaltechAUTHORS
Deposited By: George Porter
Deposited On:14 Mar 2019 22:12
Last Modified:03 Oct 2019 20:58

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