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Low-Power Circuits for Brain-Machine Interfaces

Sarpeshkar, Rahul and Wattanapanitch, Woradorn and Rapoport, Benjamin I. and Arfin, Scott K. and Baker, Michael W. and Mandal, Soumyajit and Fee, Michale S. and Musallam, Sam and Andersen, Richard A. (2007) Low-Power Circuits for Brain-Machine Interfaces. In: 2007 IEEE International Symposium on Circuits and Systems. IEEE , Piscataway, NJ, pp. 2068-2071. ISBN 1-4244-0920-9.

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This paper presents work on ultra-low-power circuits for brain-machine interfaces with applications for paralysis prosthetics, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; radio-frequency (RF) impedance modulation for low-power data telemetry; a wireless link for efficient power transfer; mixed-signal system integration for efficiency, robustness, and programmability; and circuits for wireless stimulation of neurons. Experimental results from chips that have recorded from and stimulated neurons in the zebra-finch brain and from RF power-link systems are presented. Circuit simulations that have successfully processed prerecorded data from a monkey brain and from an RF data telemetry system are also presented.

Item Type:Book Section
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Andersen, Richard A.0000-0002-7947-0472
Additional Information:© 2007 IEEE.
Record Number:CaltechAUTHORS:20190325-155828787
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Official Citation:R. Sarpeshkar et al., "Low-Power Circuits for Brain-Machine Interfaces," 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, 2007, pp. 2068-2071. doi: 10.1109/ISCAS.2007.378505
Usage Policy:No commercial reproduction, distribution, display or performance rights in this work are provided.
ID Code:94132
Deposited By: Tony Diaz
Deposited On:25 Mar 2019 23:28
Last Modified:16 Nov 2021 17:03

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