Published 1998 | Version Published
Book Section - Chapter Open

Floating-Gate MOS Synapse Transistors

  • 1. ROR icon California Institute of Technology

Contributors

Abstract

Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile floating-gate devices, such as EEPROM transistors. typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although floating-gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through Si0_2, these devices have not seen wide use as memory elements in silicon learning systems.

Additional Information

© 1998 Kluwer Academic. Lyn Dupré edited the manuscript. This work was supported by the Office of Naval Research, by the Advanced Research Projects Agency, by the Beckman Hearing Institute, by the Center for Neuromorphic Systems Engineering as a part of the National Science Foundation Engineering Research Center Program, and by the California Trade and Commerce Agency, Office of Strategic Technology.

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Identifiers

Eprint ID
53517
Resolver ID
CaltechAUTHORS:20150109-144208064

Funding

Office of Naval Research (ONR)
Advanced Research Projects Agency (ARPA)
Beckman Hearing Institute
Center for Neuromorphic Systems Engineering
California Trade and Commerce Agency, Office of Strategic Technology

Dates

Created
2015-01-09
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Updated
2021-11-10
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