Statistical
Analysis
of
Integrated
Passive
Delay
Lines
Behnam
Analui
and
Ali
Hajimiri
California
Institute
of
Technology,
Pasadena,
CA
91125
Email:
behnam
@
caltech.
edu
Abstract
Statistical properties
of
integrated
passive
LC
delay
lines are
investigated.
A new variation using
spiral
induc-
tors and
vertical parallel plate
(VPP) capacitors
is
intro-
duced
whose
delay
is primarily
determined
by
the
lateral
dimensions, resulting
in
very
accurate
and repeatable
delays.
An
MIM-based version
of
this line
is
also
fahri-
cated
for
comparison. Additionally, LC delay-based
oscillators are
implemented
to
compare
the variations
in
active
and passive delay
elements. Experimental data
is
obtained
from
measurement
of
27
and 47 sites
on
two
wafers from
two
different
process runs,
respectively.
The
measurements show
0.6% delay
variations
for
VPP-
based
delay line
compared
to
1.0%
for
its
MIM-based
counterpart.
Introduction
Accurate timing
is
the
underlying
principal used
in
communication and
computation
systems.
The
timing
accuracy directly affects
the performance
of
these sys-
tems. Integrated delay
elements are
arguably
one
of
the
most
critical building
blocks whose accuracy
and
repeat-
ability directly affect the timing
accuracy
of
digital and
mixed-mode systems. Various
forms
of active
and
pas-
sive
delay elements
have
been used
in
different circuits
and
systems
such
as
delay-based oscillators
(e.g.,
[1][3]),
delay-locked loops (DLLs)
(e.g.,
[4]),
digital-to-phase
convertors
(e.g..
[51),
and
transversal
filters
and equaliz-
ers
(e.g.,
[61).
As
the
frequency
of
these applications increases,
the
requirement
on
the absolute
accuracy
of
the delay
ele-
ments tightens.
It
is
important
to
control
the delay
of
these
elements
in
the
presence
of
variations
in
process
parameters,
supply voltage,
and temperature
to
achieve
higher yield and reliability
for
the
specified performance.
In
systems
using
active non-linear
(e.g.,
digital)
delay
elements, this
is usually
done through a feedback
system
relating the delay accuracy
to
an
external reference.
While practical
for
many digital
systems, applications
such
as
transversal
filters
and
equalizers
(e.g.,
[6])
require
linear wideband delay
elements not
to
introduce
distortion
on
the signal.
This
can
be
achieved
more
readily
by
using
integrated passive delay
lines
with prac-
tically
no
sensitivity to the
supply voltage
while
main-
taining
a
low sensitivity
to
process variations
and
temperature.
It has been
shown
[2]
that using building
blocks
that
depend
only on the lateral
dimensions,
such
as
vertical
parallel plate (VPP) capacitors,
one
can achieve
a
tighter
tolerance and better matching across
the
chip, wafer, and
process
lots.
This
is primarily
due
to the
inherently higher
accuracy
of
the
lithography
and etching processes
used
to
define
the
lateral dimensions
of
these components.
Inter-
estingly,
the
inductance
of
spiral
inductors
is
primarily
determined
by
its
lateral
dimensions, encouraging
the
design
of
passive
LC
delay
lines
using
these
lateral com-
ponents.
It eliminates the
delay dependency
on
less
accu-
rate process steps such
as
deposition and
planarization
that
control the vertical
dimensions.
This
work
presents the experimental results
of
a
set of
measurements
and statistical analysis
on
fabricated pas-
sive delay
lines
and
delay-based
oscillators.
It
verifies
low sensitivity
of
LC
delay
lines
to
process variations. In
the rest
of
the paper,
we
review
the
theory
of
LC delay
lines, and introduce
our
implementation of
integrated LC
delay
lines.
Then,
we discuss the
measurement
setup
and
results.
LC
Passive Delay
Lines
There are
several
structures comprising
inductors,
L,
and
capacitors,
C,
that
can be
used
as
delay lines. Per-
haps,
the
best known is
Bessel-Thomson
filter
[7][81
that
has
maximally
flat
delay response. However,
it
is
not
suitable
for
integration
since
it results
in
delay values that
are
small
for
today's
applications and
also
because its
component values become unreatistic
for
integration,
as
the
filter
order
increases.
Constant-k
LC
ladder structures
on
the other
hand
con-
sist
of
identical interconnected inductors
and
capacitors
in
a
ladder
form,
as
shown
in
Fig.
la.
The
ladder
is
a
lumped approximation
of
transmission
line
and
hence,
can
be
used
as
a
delay line.
It can
be
shown that the delay
of
the structure
is approximately:
where
n
is the
number of
LC
sections.
Using spiral induc-
tors
and
high density
VPP
[2]
or
MIM
capacitors
one
can
obtain large
delay
values.
Using the
image impedance
techniques,
one can
easily
calculate the
impedance
of
the
line
to
be:
.
where
Z,
=
bC
is
the characteristic
impedance
of
the line
[91.
As
can
be
seen, the
impedance becomes
imaginary
for
frequencies above
a
critical frequency
given by:
2
0
--
-
JE
6-6-1
0-7803-7842-3/03/$17.00
0
2003
IEEE
IEEE
2003
CUSTOM
INTEGRATED
CIRCUITS CONFERENCE
(3)
107
Fig.
2
Amplitude and phase
characteristics
of
constant-k
filter
sections
Delay
Line
Pawneter
Fig.
3
Differential symmetric interwound
inductors
for
one
section
of
the
delay
line
The
transmission
characteristics
of
a line composed
of
ideal
Ls
and
Cs
is
lossless upto
the
critical frequency
defined
in
(3).
Typical transmission
amplitude
and phase
characteristics
of
a constant-k
filter consisting of
ideal
Ls
and
Cs
with
proper
termination
is shown
in
Fig.
2.
Notice
that this
lossless
ladder structure
is band
limited.
While the attenuation is zero
in
the
passband,
at fre-
quencies above
mC
the
ladder
will
attenuate the
input
sig-
nal
[9].
Moreover,
in contrast
to
a continuous
transmission line, the
delay
of
an
LC
delay line
is not
constant
over
the
entire
passband
[9].
Thus, the frequency
dependent
group
delay
over the desired
range
should be
measured
to
fully
characterize the
line.
The
LC
delay
line can
be
designed in a differential form
as
shown
in
Fig.
Ib.
In such circuits,
the differential
inductors can be interwound
in
order
to
benefit from
mutual inductance
of
the
two.
Therefore, larger
value
inductances will
be
achievable
with
same
(or even
smaller)
aredsize.
It can
be
shown that
if two
equal
dif-
ferential inductors with value
L
are intenvound
with
mutual inductance
of
k
(with
proper
sign),
the
effective
inductance value
for
each
will
be
(I+k)L.
We have taken
advantage
of
this
fact
in
our
implementation
of
the delay
lines.
LC
Delay Line Implementation
Two sets
of
LC
delay lines are implemented
in
the
form
of
differential constant-k
filters
in
a
5-metal
SiGe
BiC-
MOS process
in
two
different
process runs. We will
refer
to
these two
process
runs
by
PR1 and
PR2.
The
differen-
tial inductors
are implemented using coupled
inductors
and have
1.25
interwound
turns
in
the
top
metal.
Fig.
3
shows the symmetric
layout
of the inductors. Inductors
are simulated using
a
2.5D
electromagnetic simulator
over
desired range
of
frequencies.
The
first set
of
delay lines
use
MIM capacitors and con-
sist
of
24
LC
sections
in
PRI.
In
the second set,
the
VPP
capacitors
are
used instead
of
the
MIMs.
It
has
19
LC
VOlW
Fig.
4
Delay-based
oscillator
for
testing passive
delay lines
sections
and
was
fabricated in
PR2. Based
on
our
earlier
discussion,
we expect
this
VPP-based delay
line
to
show
smaller delay
variations
compared
to
its MIM-based
counterpart.
In
VPP
capacitors,
the
distance
of
adjacent
parallel plates
of
the capacitors are
chosen to be larger
than the
minimum allowable spacing
between adjacent
metals
to
reduce the
effect
of
lateral surface roughness
on
the capacitor
value.
The
increased fringe capacitance
is
modelled accurately with
electromagnetic
simulations.
In addition to
standalone passive
delay
structures, a
delay-based oscillator
is
made
in
PR2
with
6
sections
of
similar
LC
delay lines
(with
MIM
capacitors),
as
shown
in
Fig.
4.
The
buffer
and
the inverter are
conventional
ECL
gates. Post-layout
simulations
taking various para-
sitic effects into account predict an oscillation frequency
of
4.8
GHz.
The
oscillator
core
is isolated from the
output
by buffers
desensitizing
the
frequency
to
the
load
and
trace
variations.
TABLE
I
summarizes
the
parameters
and
simulation
results of the delay
lines.
TABLE
1
Summary
of Delay
Line Parameters
Experimental Results and Analysis
Standalone delay structures
using
MIMs and VPPs
and
the
oscillators
in
PR2 are
tested
with
direct
on
wafer
probing.
The
results
are
summarized
in
the
following
sub-sections.
A.
Measurement
Accuracy and Repearability
27
MIM-based
delay lines
in
PRI
and
47
VPP-based
delay lines
in
PRZ
were characterized
using
an
Agilent
Technologies
E8364A
network
analyzer.
To
ensure con-
stant
environmental conditions
(including temperature
and measurement
setup
variations) during the
measure-
ment
of
all
74
sites,
a set
of
preliminary
experiments
were
performed.
Six random sites
were
selected
as
wit-
ness
cases and were measured three times each
at differ-
ent
times
during the measurement.
Then,
the
results
for
each
site
were compared.
The
observed
variations were
always
less
than 0.05% indicating
the measurement error
and the degree of its
repeatability.
This
very high repeat-
ability
of
results indicates minimum changes
in
the
con-
ditions
of
the
experiments.
108
6-6-2
0
-
-10
-20
9
Q
E
.-
-&
-30
4
-40
-50
0.
I
I
to
IM)
f
[GHz]
Fig.
5
Magnitude
of the
S-parameters
of one
MEM-based
standalone delay line
0
Fig.
6
Collective group delays
of
27
standalone MIM-based
delay lines
B.
Standalone
Delay
Lines:
S-parameters
parameters
of
MIM-based
and VPP-based delay lines
were
measured.
A
sample
result
for
a
MIM-based delay
line,
plotted in Fig.
5
shows
SI,
<
-12dB
(upto
30
GHz).
Similar
measurements for
VPP-based
delay
lines
show
SI/
e
-16dB
(1.5GHz
<f<
20GHr).
They indicate that
the
delay line
characteristic impedances are very close
to
50
Cl
over
that
wide range
of
frequencies.
The
low
frequency
loss
of
MIM-based
delay
line
is
1.2
dB
and
its
3-dB
bandwidth
is
7.5
GHz.
C.
The group delays of the whole ensemble
for
both MIM-
based and VPP-based lines are plotted
in
Fig.
6
and
Fig.
7,
respectively.
The
dominant
source
of
variations over
different
wafer
sites
for
samples
in
MIM-based lines
is
the tolerance
of
MIM capacitors.
The
reported
MIYtol-
erance
in
this
process technology
is
fO.l5fF/pm
.
It
translates
to a total
tolerance
of
dC=18.8jF
for
the MlMs
that
we
used.
The
time delay variations
per
section
can
be
approximated from
(I)
as
follows:
Magnitude
of
SI]
and
Standalone
Delay
Lines:
Group
Delay
a=,
ac
ATD
=
-
.
AC
ATu
-
I
AC
-
-
-
.
-
=
0.04
Tu
2
C
The
normalized standard deviations of
group
delay (nor-
malized
to
the
mean
group delay
at
corresponding
fre-
quency) for MIM-based and VPP-based lines
are
plotted
in
Fig.
8.
The
variations
for
MIM-based lines
are
within
the
tolerance
of
the MIM capacitors
in
(5).
The
delay
lines
with
VPP capacitors are almost twice more accurate
across
most
of
the
frequency range.
This corresponds
to
a
................
...
-
-3
1
g
~XlO
0
Fig.
7
Collective
group
delays
of
47
standalone
VPP-based
delay
lines
Fig.
8
Normalized standard
deviations
for
group
delays
of
standalone delay
lines
factor
of
3.3
improved tolerance
for
the VPPs
in
agree-
ment with
[2].
TABLE
2
compares
the average
low
fre-
quency group delays and the average normalized
standard deviations
of
that
in
both cases. Again,
it
can
be
TABLE
2
Statistical
comoarisun
for
MIM
and
VPP-based
lines
MIM
Ion
[wq
pup
delq
I
56
.7ps
I
0.572~~
[
101%
VPP
I,,”
ireY
Rr~up
dd0)
I
52.14
pr
I
0.m
p~
I
o
59%
seen
hat
the VPP-based delay
lino
3re
almost
twice
mnre
accurate. Fig.
9
shows distribution
of
normalized
delay
at
I
GHz
for
both MIM- and VPP-based
delay
lines.
D.
Delay-Based
O.sci//atfm
Adelay-based oscillaror
is fabricated similar
to
the
one
in
Fig.
4.
The
measured frequency
of
the oscillator
will
be
a direct indicative
of
the
aggregate
time
delay
of
the
pabbive
delay line
and cascaded active
circuiy.
An
out-
put
buffer
is added
to
drive
50
i2
load.
Total
of
47
bites
are measured from
two
different
wafen.
The
tu0
wafers
have
received different emitter processes. one resulting
in
an improved emitter resistance. Therefore.
the
active
ele-
ments
in
1\10
sets are different.
The oscillation frequencies are measured
with
on
wafer
probing
using
HP
85638
spectrum
analyzer
and HP
53150A
frequency counter.
It
is notewonhy
that the
fre-
quenq
is recorded
after
each ossil lator stabilizes. Stabili-
zatinn time
constant
after start-up
is
measured
to
be
around
30
secThe frequency
mean
3nd
standard deviation
6-6-3
109
Fig.
10
Die
photo
of
19-section
VPP-based
LC
delay
line
......................
...........................
98%
99%
IWB
101%
102%
Normalized
Delay
Fig.
9
Distributions
of
normalized
delay
at
IGHz
for
both
MIM
and VPP-based delay
lines
are
listed
in
TABLE
3.
The
measurement
is
in
good
agreement
with
the simulation results. Overall
data
shows
0.8%
variability
in
center
frequency
with respect
to mean.
The
mean time
delay
around
the
loop
is
105.2
ps
and
its
corresponding normalized standard deviation
is
0.85%.
The loop delay
is
calculated from
half
of
the
inverse
of
oscillation
frequency
for
each
oscillator.
TABLE
3
Statistical analysis
of
the
oscillators
.The
die
photo
of
the
VPP-based
line, MIM-based line
and the
oscillator are
shown
in Fig.
10-12,
respectively.
The
passive delay
lines
are
dominating
the area.
The
spi-
ral
inductors
are
formed
in
a loop
in
the
oscillator
to
avoid
long
interconnect lines.
The
capacitors are
located
in
between
the
inductors.
Inductor
size
is
150pmx
150pm
The
total chip dimensions
for
the
oscillator
are
900pm
x
560pm
,
Conclusions
In
this paper
a
set
of experiments
are
performed
to
investigate the
sensitivity
of
two
different types
of
inte-
grated LC delay
lines
to
process variations.
The
compo-
nent values
of
such integrated delay lines depends
only
on
accuracy
of
lithography
and
etching processes in
the
case
where
VPP capacitors
are
used. Delay
lines
imple-
mented using such
LC
structures
are
shown
to
he
more
accurate.
The
measurements based
on
47
VPP-based
delay line chips
and
27
MIM-based delay
line
chips
indi-
cates
twice
as
large variations
in
group
delay
for
MIM-
based delay lines.
In
summary,
passive
LC
delay lines
with
VPP capacitors are
best
structures
for
implementing
linear passive delay
lines with low
sensitivity
to
process
variations
and
no
sensitivity
to
supply
variations.
Fig.
II
Die photo
of
24-section
MlM-based
LC
delay
line
Fig.
12
Die Photo
of the delay-based
oscillator
with
6-section
differential
LC
delay line
Acknowledgments
The
authors acknowledge
M.
Owrang
for
assistance
in
measurement
and
valuable feedbacks.
They are
also
grateful
to
A.
Komijani,
S.
Mandegaran, and
I.
Buck-
Walter
from
Caltecb’s
CHIC group
for
useful
discussions
and
helps.
They
thank
Lee
Center
for
Advanced Net-
working,
IBM,
and Agilent Technologies
for
supporting
this
project.
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