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Supplementary Information: Topological phonon transport in an optomechanical
system
Hengjiang Ren,
1, 2,
Tirth Shah,
3, 4,
Hannes Pfeifer,
3,
Christian
Brendel,
3
Vittorio Peano,
3
Florian Marquardt,
3, 4
and Oskar Painter
1, 2, 5
1
Thomas J. Watson, Sr., Laboratory of Applied Physics and Kavli Nanoscience Institute,
California Institute of Technology, Pasadena, CA 91125, USA
2
Institute for Quantum Information and Matter,
California Institute of Technology, Pasadena, CA 91125, USA
3
Max Planck Institute for the Science of Light, Staudtstr. 2, 91058 Erlangen, Germany
4
Department of Physics, Friedrich-Alexander Universit ̈at Erlangen-N ̈urnberg, Staudtstr. 7, 91058 Erlangen, Germany
5
AWS Center for Quantum Computing, Pasadena, CA 91125, USA.
§
(Dated: June 13, 2022)
These authors contributed equally to this work.; Present Address: Institute of High Performance Computing, Agency for Science,
Technology and Research (A*STAR), Singapore 138632, and Anyon Computing Inc, Dover, DE 19901, USA
These authors contributed equally to this work.
Present Address: Institut f ̈ur Angewandte Physik, Universit ̈at Bonn, Wegelerstr. 8, 53115 Bonn, Germany
§
opainter@caltech.edu
2
Supplementary Note 1. FINITE ELEMENT SIMULATIONS
In Fig.1 of Main Text, we show the phononic band structures and the photonic crystal cavity modes. The mechanical
normal modes are obtained by numerically solving the eigenvalue equation,
div
[
C
:
[
grad
Q
n
(
r
) + (grad
Q
n
(
r
))
T
]]
=
2Ω
2
n
ρ
(
r
)
Q
n
(
r
)
.
(1)
Here and throughout the Supplemental Information,
Q
n
(
r
) (
Q
k
,n
(
r
)) denotes the three-dimensional mechanical dis-
placement
Q
n
(
r
,
t
) = Re
[
Q
n
(
r
)
·
e
i
n
t
]
for a normal mode (Bloch wave) with eigenfrequency Ω
n
. Moreover,
C
is
the elasticity tensor,
ρ
the mass density, and : is a symbol for the tensor product, where [
C
: grad
ψ
]
ij
=
C
ijkl
l
ψ
k
.
Optically, our structure is described by the Maxwell’s equations, which in the absence of a source, takes the form
of the following eigenvalue equation
c
2
curl
[
1
ε
(
r
)
curl
H
n
(
r
)
]
=
ω
2
n
H
n
(
r
)
.
(2)
where
H
n
(
r
) denotes the magnetic field
H
n
(
r
,
t
) = Re
[
H
n
(
r
)
·
e
n
t
]
for the photonic crystal cavity mode with
eigenfrequency
ω
n
.
c
is the speed of light in vacuum, and
ε
(
r
) is the relative permittivity of the medium. Both of
these equations are solved with the finite-element method (FEM) solver [1].
Supplementary Note 2. DEVICE FABRICATION AND MEASUREMENT SETUP
The devices were fabricated on silicon-on-insulator (SOI) wafers from SEH, with a device layer Si thickness 220 nm,
buried oxide (BOX) layer 3
μ
m, handle Si thickness 500
μ
m, crystal orientation
1
,
0
,
0
, resistivity
ρ >
3000 Ω
·
cm,
diced into die of 5
×
10 mm. Silicon-on-insulator is a natural choice of substrate as it allows the ease of fabrication
of suspended nanoscale structures within the thin membrane of the silicon device layer by simply removing or un-
dercutting the buried oxide layer, and the standard fabrication processes for SOI are very mature in both industrial
and academic applications. In its simplest form this process involves only a single layer of lithography to fabricate
suspended silicon structures. An overview of the fabrication process for the devices is:
1. Pre-cleaning of the chip. This step prepares the substrate chip for application of resist. Chips will typically
retain some protective coating after the wafer-dicing process, either in the form of an adhesive film or a layer of
photoresist. In either case, a solvent rinse in acetone (ACE) followed by isopropanol (IPA) is usually sufficient
to obtain a clean chip surface.
2. Spinning and baking of electron-beam (e-beam) resist, spin speed 8000 rpm, ramp speed 2500rpm/s, spin time
60s. We typically use a ZEON ZEP-520A e-beam resist for its high resolution and high selectivity against
common plasma etch chemistries. The resist is hardened by baking using a hot-plate, 180
C, 2 minutes.
3. Electron-beam (e-beam) lithography exposure. The device pattern is defined in the resist using e-beam lithog-
raphy, including proximity effect corrections to refine the dose exposing the resist. The electron beam dose is
180
μ
C/cm, beam voltage is 100keV, beam current is 140pA, resolution/beam step size is 1
2
.
5 nm.
4. Resist development. The chip is submerged in a developing solvent to relieve the patterns, in the case of
ZEP-520A the developer used here is ZED-N50, 2 minutes 30 seconds. Followed by MIBK rinse, 30 seconds.
5. Plasma etching. Inductively-coupled plasma reactive-ion etching (ICP-RIE) is used to transfer the device pattern
from the resist into the silicon layer. Etching parameters are listed in Supplementary Table I.
6. Resist stripping. A chemical cleaning is performed to remove the resist layer, typically by submerging the chip
in a piranha solution (3:1 sulfuric acid to hydrogen peroxide), in which a highly exothermic reaction chemically
burns organics such as resist from the chip and mechanically scrubs debris.
7. Oxide undercutting or device layer
release
. To remove the buried oxide in the vicinity of the OMC device,
hydrofluoric acid (HF) is used as an etchant. This is typically performed using anhydrous vapor-HF.
Note that the mechanical frequencies are changed in the tree geometries compared to triangle geometries, because
parameters of snowflake structures (
a
m
,
r
and
w
) in the tree geometries have been scaled by an overall factor of 1
.
01
with respect to the triangle samples (the photonic crystal properties were kept identical).