of 6
Superconducting qubits on silicon substrates for quantum device integration
Andrew J. Keller,
1, 2
Paul B. Dieterle,
1, 2
Michael Fang,
1, 2
Brett Berger,
1, 2
Johannes M. Fink,
1, 2, 3
and Oskar Painter
1, 2
1
Kavli Nanoscience Institute and Thomas J. Watson Laboratory of Applied Physics,
California Institute of Technology, Pasadena, CA 91125
2
Institute of Quantum Information and Matter, California Institute of Technology, Pasadena, CA 91125
3
Institute of Science and Technology Austria, 3400 Klosterneuburg, Austria
(Dated: April 4, 2017)
We present the fabrication and characterization of transmon qubits formed from aluminum Joseph-
son junctions on two different silicon-based substrates: (i) high-resistivity silicon (Si) and (ii) silicon-
on-insulator (SOI). Key to the qubit fabrication process is the use of an anhydrous hydrofluoric vapor
process which removes silicon surface oxides without attacking aluminum, and in the case of SOI
substrates, selectively removes the lossy buried oxide underneath the qubit region. For qubits with a
transition frequency of approximately 5 GHz we find qubit lifetimes and coherence times comparable
to those attainable on sapphire substrates (
T
1
,
Si
= 27
μ
s,
T
2
,
Si
= 6.6
μ
s;
T
1
,
SOI
= 3.5
μ
s,
T
2
,
SOI
=
2.2
μ
s). This qubit fabrication process in principle permits co-fabrication of silicon photonic and
mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical
transducers for quantum networking of superconducting microwave quantum circuits.
PACS numbers: 03.67.Lx, 84.40.Dc, 85.25.-j
In recent years, significant developments in experimen-
tal quantum information science [1, 2] have been realized
using microwave superconducting qubit hardware. These
devices, consisting of Josephson junctions (JJs) and lin-
ear circuit elements, are typically coupled to high-
Q
su-
perconducting microwave cavities, which realizes the mi-
crowave analog of cavity QED—so-called circuit QED [3–
5]. The advent of the transmon qubit [6–8] has provided
a robust and scalable circuit QED building block. Lever-
aging small mode volumes and large vacuum coupling
rates, circuit QED systems have been put into the regime
of strong coupling, [5, 9] realized state-of-the-art gate fi-
delities, [10] and utilized to perform quantum error de-
tection and correction. [11, 12]
Interfacing the circuit QED toolbox with other sys-
tems of physical or technological interest – cavity op-
tomechanical systems, for example [13, 14] – requires
scalable fabrication techniques on compatible materials
systems. Much work within the circuit QED community
has focused on developing fabrication methods that re-
alize long qubit lifetimes and small dephasing rates [15–
17]. Owing to sapphire’s good microwave properties, this
work has primarily utilized the aluminum-on-sapphire
(AOS) materials system. Using the AOS material system
two primary approaches have emerged: the so-called pla-
nar approach wherein qubits are coupled to on-chip res-
onators [18] and the 3D cavity approach wherein qubits
are coupled to 3D box cavities [19]. Whereas the former
affords higher device densities and more integration, the
latter yields longer coherence times.
Here, we demonstrate scalable fabrication techniques
for planar silicon-based superconducting circuits [20–
22] that obtain similar transmon qubit coherence times
and gate fidelities as their planar sapphire counter-
parts [10, 18]. We note that similar work has recently
been performed with silicon-based qubits in the context
of 3D cavities [23]. Additionally, we present the fabrica-
tion and characterization of a superconducting qubit on
silicon-on-insulator (SOI) with a coherence time which is
a factor of 20 improvement over prior work in this ma-
terial system [24]. These SOI qubit fabrication methods
not only realize high quality qubits, but are also compati-
ble with the integration of other photonic, electronic, and
MEMS components on the same SOI substrate.
Our qubit design (pictured in Fig. 1(b), and shown
schematically in Fig. 2(c)) is based on the Xmon
qubit. [18] In both our high-resistivity silicon (Si) and
SOI devices, a long rectangular capacitor is capacitively
coupled to both a readout resonator and an XY-control
line; the capacitor is connected to ground through a
SQUID loop (Fig. 1(c)) that is inductively coupled to
a DC control line, which allows for frequency tuning of
the qubit. [18] Our readout resonator, consisting of a
λ/
4
coplanar waveguide resonator, is inductively coupled to
a transmission line, which allows for dispersive readout
of the qubit. [18] We realize (Si, SOI) as-measured pa-
rameters of:
f
q
=
ω
q
/
2
π
= (4
.
962
,
5
.
652) GHz,
η/
2
π
=
(
260
,
300) MHz,
ω
r
/
2
π
= (6
.
868
,
7
.
143) GHz, and
χ/
2
π
= (1
.
2
,
3
.
5) MHz, where
ω
q
=
ω
10
is the qubit tran-
sition frequency,
η
= (
ω
21
ω
10
) is the anharmonicity,
ω
r
is the readout resonator frequency, and 2
χ
=
ω
r,
|
0
ω
r,
|
1
is the dispersive shift. These measured values imply a
Josephson energy
E
J
/h
= (13
.
1
,
14
.
8) GHz in the trans-
mon limit (
E
J

E
C
) where ̄
q
8
E
J
E
C
E
C
and
the charging energy
E
C
≈ −
̄
, as well as a vacuum
qubit-resonator coupling rate
g/
2
π
= (135
,
177) MHz
where
g
χ
(1 + ∆
) and ∆ =
ω
q
ω
r
. Our read-
out resonators have intrinsic and extrinsic coupling
Q
s of
Q
i
= (5
.
8
,
45
.
8)
×
10
3
and
Q
e
= (12
.
9
,
6
.
1)
×
10
3
, respec-
tively, measured at single-digit intracavity photon num-
bers. These values are close to the designed and expected
values, except for the intrinsic
Q
i
of the read-out res-
arXiv:1703.10195v2 [quant-ph] 3 Apr 2017
2
XY control
Z control
readout
200 μm
(b)
(c)
(d)
50 μm
2 μm
Si
SiO
2
(a)
C
4
F
8
/SF
6
dry etch (*)
Al ground plane
evaporation
junction
evaporation
ion mill, bandage
evaporation
HF vapor
release (*)
ground plane
qubit cap.
FIG. 1. Qubit fabrication process and SEM images of the SOI device. (a) Five step fabrication process as detailed in the text.
Steps labeled (*) are omitted for the Si qubit process. (b) SEM image of an SOI qubit. The light (dark) gray regions are Al
(exposed Si). The yellow outline demarcates the etch front of the HF vapor release, which extends
100
μ
m under the ground
plane so as to isolate the qubit from the lossy Si-SiO
2
interface. The red box denotes the SQUID loop region of the device.
(c) Zoom-in image of the SQUID loop, formed by a double angle evaporation process. The green box bounds one junction.
“Bandage” regions described in the main text are visible as darker squares on both the qubit capacitor and the ground plane.
(d) Zoom-in of an individual Josephson junction. Each junction has an approximate area of (200 nm)
2
, corresponding to a
zero-bias Josephson Inductance of
L
J,
0
= 22 nH per junction under the conditions described in the main text. The lattice of
tiny dark circles faintly visible here are the etched holes that allow for HF vapor release. An orange arrow points to one such
hole.
onator on Si. This value is more then two-orders of mag-
nitude smaller than expected from previous resonator-
only tests we have performed on Si. Evidence of fre-
quency jitter in the read-out resonator of this sample was
observed, which may explain an under-estimate of the
Q
i
from the swept frequency measurement used here.
Our fabrication process is a multi-layer process pic-
tured in Fig. 1(a). We begin with a 10 mm
×
10 mm
chip of either Si [Float zone (FZ) grown, 525
μ
m thick-
ness,
>
10 kOhm-cm resistivity] or SOI [Si device layer:
FZ grown, 220 nm,
>
3 kOhm-cm; BOX layer: 3
μ
m,
silicon dioxide; Si handle: Czochralski grown, 750
μ
m,
>
5 kOhm-cm]. We then perform the following main
fabrication steps (from left to right in Fig. 1(a)): (i)
C
4
F
8
/SF
6
inductively coupled plasma reactive ion etch
(ICP-RIE) of 50 nm radius holes through the device layer
to allow for release in step (v) below; (ii) electron beam
evaporation of 120 nm Al at 1 nm/s to define a ground
plane, the qubit capacitor, and the readout resonator;
(iii) double-angle electron beam evaporation of 60 nm
and 120 nm of Al at 1 nm/s with an intervening 20 minute
oxidation at 5 mbar and subsequent 2 minute oxidation
at 10 mbar to forms the JJs; (iv) 5 minute argon ion mill
and 140 nm Al evaporation to form a “bandage” layer
that electrically contacts the Al layers defined in step (ii)
and (iii); (v) HF vapor etch of the underlying BOX layer.
After steps (ii-iv), a liftoff process was performed in
n-methyl-2-pyrrolidone at 80
C for two hours. Steps (i)
and (v) are omitted for Si devices as they do not require
a release. In (i-iv), we use electron beam lithography to
pattern our resist. The above process is similar to that
described elsewhere [25, 26] and, for SOI samples, yields a
device layer that is partially suspended above the handle
wafer. As highlighted by the yellow boundary line in the
scanning electron microscope image of Fig. 1(b), we etch
100
μ
m into the BOX layer such that the circuit is far
from the lossy Si/SiO
2
interface. [25]
We characterize each qubit in a
3
He/
4
He dry dilu-
tion refrigerator with base temperature of
T
f
7 mK
using frequency-domain and time-domain spectroscopy.
We begin with frequency-domain characterization and
measure transmission (
S
21
) through a coplanar waveg-
uide feedline using a two-port vector network analyzer
(VNA). The Z control line is used to carry a small cur-
rent which produces an external flux bias, Φ
ext
, in the
SQUID loop of the qubit, thereby tuning the qubit tran-
sition frequency,
f
q
. For a given Φ
ext
, we identify
f
q
and
transitions to higher levels (from which we extract
η
) by
sweeping a continuous-wave (CW) microwave tone ap-
plied to the XY drive line and monitoring the resonator
response. [27]
Having identified device parameters, we switch over
3
Mixing
chamber
plate
9.6
GHz
HEMT
4 K plate
50 K plate
300 K
40 dB
20 dB
20 dB
I
Q
40 dB
225
MHz
7.5
GHz
9.6
GHz
7.5
GHz
64
kHz
AWG
1
2
4
7.5
GHz
I
Q
-6 dB
I
Q
30 dB
+
+
1
2
+
4
XY
3
+
3
2-channel
digitizer
500
MHz
500
MHz
Read
(a)
(c)
(b)
XY line
Feedline
Z line
Qubit
λ/4 readout
resonator
700 μm
FIG. 2.
(a) Time-domain measurement scheme. Near the
top, Gaussian filters are indicated by enclosed Gaussian line-
shapes (lines
i
and
̄
i
are filtered individually). CW microwave
sources with
Z
= 50 Ω are indicated by the ac voltage sym-
bols. The microwave source used for readout is followed
by a power divider (we use just two ports and terminate
others with 50 Ω). Attenuators are indicated by rectangles
with labeled power attenuation. Capacitor symbols show in-
ner/outer DC blocks. All low pass filters are reflective except
for the 64 kHz filter, which is a dissipative RCR filter (R =
499 Ω, C = 10 nF). (b) Photograph of 1 cm
2
chip wire-bonded
to PCB. (c) Schematic of the Si and SOI Xmon circuit, in-
cluding layut of read-out resonator, control lines, and cavity
feedline.
to time-domain characterization, using the measurement
setup summarized in Fig. 2 (for details see App. A).
We characterize each qubit using dispersive readout [28]
(Fig. 3) with Φ
ext
set so that the qubit is at a first-order
flux-insensitive point. [6, 18] In this projective readout
scheme, a sample from one of two distributions in the
I-Q plane is measured depending on whether the qubit
is projected into the ground or excited state. We make
a binary discrimination for each single measurement of
an arbitrary pulse sequence (1 for excited qubit state
|
1
,
or 0 for ground qubit state
|
0
), and average at least
Normed |1> pop.
(a)
(c)
(e)
(d)
(b)
(f)
τ
Duration
(μs)
τ
Duration
(μs)
τ
Delay (μs)
τ
Delay (μs)
τ
Delay (μs)
τ
Delay (μs)
τ
Read
τ
Read
Xπ/2 Xπ/2
τ
Read
FIG. 3.
Qubit characterization (left column: Si; right col-
umn: SOI). (a,b) Excited state population (normalized to the
unit interval) as a function of XY drive frequency and pulse
duration
τ
exhibits a chevron pattern typical of a qubit un-
dergoing Rabi oscillations. (c,d) Natural log of the excited
state population, normalized to the unit interval, shows ex-
ponential decay as a function of waiting time
τ
with lifetimes
T
1
,
Si
= 27
μ
s and
T
1
,
SOI
= 3.5
μ
s. (e,f) By applying two off-
resonance
π/
2 pulses with a variable intervening delay
τ
, the
excited state population shows Ramsey oscillations (points
are data, blue trace is fit). The decay of the envelope yields
coherence times
T
2
,
Si
= 6.6
μ
s and
T
2
,
SOI
= 2.2
μ
s. In all
cases, we use a rectangle-windowed readout pulse with 500 ns
duration, and in most cases we use a 30 ns X
π
and X
π/
2
pulse
(45 ns in (c)).
10
4
such values to determine excited state population.
The sub-unity visibility (e.g., see Fig. 3(e,f)) primarily
reflects imperfect readout fidelity for both Si and SOI
devices. [29]
To characterize our gate fidelities, we utilized Clif-
ford group randomized benchmarking, [10, 30, 31] shown
schematically in Fig. 4(a,b). For the Si sample Fig. 4(c),
we measured two gates (
X
π/
2
and
X
π
) while for SOI
(Fig. 4(d)), we measured three (
X
π
,
X
π/
2
, and
Y
π
). We
realize average gate fidelities of
̄
f
(
C
) = 0
.
9952(5) on Si
and 0
.
9860(2) on SOI as well as individual gate fidelities
of
>
0
.
992 for all measured gates on Si and SOI. It should
be noted that these gates have not yet been optimized to
4
0
20
40
60
80
100
10
-2
10
-1
0
20
40
60
80
100
10
-1
1





1



(
(
(
(
N
N
X
π
C
i
C
i
C
j
1
i
C
j
1
i
j
0
i
j
0
i
N
1 3 5 7 9
log
10
P
1
(a)
(b)
(c)
(d)
0
N
0 20 40 60 80 100
excited state population
(log
10
scale, arb. o"set)
SOI
f(X
π/2
) = 0.9943(3)
f(C) = 0.9860(2)
f(X
π
) = 0.9932(3)
f(Y
π
) = 0.9925(6)
HR-Si
N
0 20 40 60 80 100
f(X
π/2
) = 0.996(2)
f(C) = 0.9952(5)
f(X
π
) = 0.9961(6)
excited state population
(log
10
scale, arb. o"set)
Nlog
10
[p]
Nlog
10
[p
X
π
]
FIG. 4. Randomized benchmarking. (a) A schematic of Clif-
ford Group randomized benchmarking, described in detail in
App. B. (b) A plot of the excited state probability as a func-
tion of
N
reveals the gate fidelity through the slope of the
resultant line on a semilog plot and the relations described
in App. B. The limit of perfect fidelity is shown as a dashed
line. (c, d) Plots of the gate fidelity (with an arbitrary off-
set given by the readout fidelity) as a function of
N
for both
Si (c) and SOI (d) qubits. Error bars in the plots represent
1 standard error in the measurements averaged over (40
,
50)
random Clifford sequences on (Si,SOI). Error bars in the gate
fidelities represent 1 standard deviation of
f
due to the sta-
tistical uncertainty of the parameter
p
in the exponential fit.
avoid phase errors or leakage outside the computational
basis [32].
Our measurement of
T
1
,
Si
= 27
μ
s for our Si qubit
is noteworthy, especially given the simplicity of our
design and fabrication process. We can estimate the
Purcell-limited
T
1
by the simplistic single-mode estimate
(∆
/g
)
2
r
, where
κ
r
=
ω
r
/Q
and 1
/Q
= 1
/Q
i
+ 1
/Q
e
.
This yields 18.5
μ
s (8.5
μ
s) for the Si (SOI) qubit of this
work, implying that: (i) the estimate is inaccurate, since
we measure a larger-than-estimated
T
1
for Si (a more con-
servative estimate which assumes we are indeed under-
estimating
Q
i
due to frequency jitter and takes
Q
Q
e
,
yields a Purcell-limited
T
1
of 57
μ
s), and (ii) incorporat-
ing an on-chip Purcell filter may well improve our qubit
lifetimes. [33, 34] Also, regarding the measured
T
2
values,
since obtaining these measurements we have identified
and resolved some grounding issues in our measurement
setup that likely contributed to excess flux noise coming
from 60 Hz currents on our flux bias line. We anticipate
that these improvements may even be important at the
first-order flux insensitive point.
In terms of the impact of the SOI device layer proper-
ties or various fabrication steps on the resulting qubit de-
coherence times, further systematic studies are required.
In particular, the importance of using the vapor HF etch
to remove native oxides and (temporarily) passivate the
Si surface before every evaporation step of aluminum
on the Si layer (including right before the double an-
gle evaporation used to form the JJs), needs to be clar-
ified further. Also, any residual effects of the underly-
ing BOX layer needs to be ruled out through system-
atic studies of qubit coherence versus undercut extent,
in conjunction with 3D numerical modeling to deter-
mine more optimized qubit and membrane geometries.
Even while the precise physical and materials limita-
tions of our system are unclear, current coherence times
are sufficient for many quantum simulation and quan-
tum optics experiments. Meanwhile, our realization of a
highly coherent SOI qubit represents an essential build-
ing block for hybrid electro-opto-mechanical systems on
SOI. Already, electromechanical and optomechanical co-
herent transduction bandwidths exceed the bandwidth
of our qubit by a factor of two [14, 25, 35], a prerequi-
site for high-fidelity, bi-directional microwave-to-optical
quantum state transduction—an interesting and chal-
lenging research program in its own right, with many
potential realizations.
Overall, our fabrication and measurements of planar
qubits on silicon and SOI represent a modest but impor-
tant technical stepping stone on the path to a variety
of potential quantum information and quantum science
goals. Taken together with complementary advances in
the fields of cavity opto- and electro-mechanics [14, 36],
and in the context of competing systems [18, 23], we are
optimistic about the potential for hybrid quantum sys-
tems and circuit QED on silicon and silicon-on-insulator
platforms.
ACKNOWLEDGMENTS
We gratefully acknowledge the Martinis Group
(UCSB/Google) for their amplifier and filter designs as
well as Dan Vestyck at SPTS for his support of our uEtch
HF vapor tool. This work was supported by the AFOSR
MURI Quantum Photonic Matter (grant 16RT0696), the
AFOSR MURI Wiring Quantum Networks with Mechan-
ical Transducers (grant FA9550-15-1-0015), the Institute
for Quantum Information and Matter, an NSF Physics
Frontiers Center (grant PHY-1125565) with support of
the Gordon and Betty Moore Foundation, and the Kavli
Nanoscience Institute at Caltech. A.J.K. acknowledges
an IQIM Postdoctoral Fellowship.
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Appendix A: Measurement setup
A Tektronix AWG5014C arbitrary waveform generator
(AWG) generates shaped in-phase (I) and quadrature (Q)
pulses at IF = 100 MHz for both qubit readout and XY
drive. Each output of the AWG passes through its own
home-made dissipative Gaussian filter with 320 MHz cut-
off. The waveforms are each amplified with a home-made
6
differential amplifier and passed to the I and Q ports of
IQ mixers (Marki IQ-0307MXP for the XY drive, IQ-
0409MXP for readout). Carrier tones are supplied by
CW microwave sources (Rohde & Schwarz SMB100A)
to the local oscillator (LO) ports of the mixers. As a
result, the readout and XY pulses are single-sideband-
upconverted to microwave frequencies. We attenuate
and filter these signals at several temperature stages of a
cryogen-free dilution refrigerator.
Flux biasing is provided by a programmable DC source
(Yokogawa GS200) which is filtered at 4 K (Therma-uD-
25G from Aivon Oy, Helsinki, Finland) and again at the
mixing chamber plate with a reflective microwave filter
(Minicircuits).
The DC and AC signals reach the device, which is
mounted on a gold-plated PCB inside a copper box inside
two concentric magnetic shields (Magnetic Shields Ltd.,
Staplehurst, UK) consisting of 1.5 mm thick Cryophy ma-
terial heat-treated to MSL1154-HTC specification. The
inner shield is 51mm ID by 168mm high and the outer
shield is 67mm ID by 185mm high. The copper box and
magnetic shields are mounted to a copper coldfinger at-
tached to the mixing chamber plate. A shield on the
mixing chamber is painted in an infrared-absorbing car-
bon/silica/epoxy mixture to minimize quasiparticle gen-
eration in the aluminum. [37, 38]
The output is protected from room-temperature noise
by two circulators (Raditek RADC-4-8-Cryo-0.02-4K-
S23-1WR-b) and at 4 K, a HEMT (Low Noise Factory
LNF-LNC4
8C) amplifies by 42 dB, with 68 dB further
amplification at room temperature. We used two room-
temperature power amplifiers, a Miteq AFS42-00101200-
22-10P-42 with 50 dB of gain and a home-made amplifier
with 18 dB of gain designed by the Martinis group. The
readout signal is then downconverted and the resulting
I and Q are simultaneously digitized using a 1GS/s 2-
channel PCIe digitizer (AlazarTech ATS9870). In soft-
ware, the I and Q are mixed with 100 MHz tones to yield
a single point in the I-Q plane for a single readout pulse.
The semirigid coaxial cable in our fridge is stainless-
stainless .085” above the 4 K plate and NbTi-NbTi .085”
below.
Appendix B: Randomized benchmarking
In Clifford group randomized benchmarking proto-
cols, [10, 30, 31] a qubit initialized in its ground state
has 2
N
gates performed on it—
N
random gates from
the Clifford group (labeled
C
i
) interleaved with
N
of the
same Clifford gate (e.g.,
X
π
). After application of all
2
N
gates, we perform the Clifford gate that puts the
qubit in its excited state (labeled
C
|
1
) and read out
the qubit state. The probability of being in the excited
state as a function of
N
, is then compared against the
same procedure, but without
N
of the same interleaved
gate. This procedure yields two exponentials of the form
c
1
+
c
2
p
N
, the latter with depolarizing parameter ̄
p
and
the former with depolarizing parameter
p
G
. These two
parameters are related to the average Clifford group gate
fidelity,
̄
f
(
C
), and gate fidelity of interest,
f
(
G
), through
̄
f
(
C
) = 1
1
̄
p
2
and
f
(
G
) = 1
1
p
G
/
̄
p
2
. [31] For the data
presented in Fig. 4, we performed 20000 measurements
on 40 (50) random Clifford group sequences on Si (SOI).