HAJIMIRI LAYOUT - HAJieeecm04.pdf

IEEE Communications Magazine • August 2004

122

OPICS IN

IRCUITS FOR

OMMUNICATIONS

NTRODUCTION

Space is the next frontier for wireless communi-

cations as networks evolve to meet higher data

rate and quality of service requirements. It is

becoming increasingly difficult to achieve further

improvements in spectral efficiency using pure

time and frequency domain methods. Interest-

ingly, there are spatial methods that can be used

to improve data rates without the dreaded

increase in bandwidth. Therefore, exploiting the

spatial dimension for improving spectral efficien-

cy is an area of rapidly increasing interest. Multi-

ple antenna systems have been identified as one

means of effectively increasing spectral efficiency

by taking advantage of spatial directivity and

diversity, as well as array gain via the multipath

scattering present in most indoor and urban

environments. The antenna size and the spacing

between the elements are inversely proportional

to the frequency. This inspires a move to higher

frequencies to leverage spatial processing tech-

niques, as multiple antenna systems can be made

physically smaller. In addition, larger bandwidths

are available at higher frequencies. Small-sized

highly integrated low-power multiple-antenna

systems can also be used for ranging and sensing

applications such as radar.

In 2002 the FCC released the guidelines for

operation of wireless devices at 24 GHz [1]. It

permits fixed point-to-point wireless communica-

tion in the 24–24.25 GHz band subject to limita-

tions on the transmitted power and directionality

of the transmitter. The FCC has also opened up

7 GHz of bandwidth from 22–29 GHz for vehic-

ular radar applications. Short-range vehicular

radar systems are expected to play an important

role in collision prevention and driver assistance

in the future (e.g., assisted parking and blind

spot detection). The 24 GHz band already has

users, particularly in the fields of remote sensing

and astronomy. Interestingly, in addition to spec-

ifications limiting transmitted power to different

levels at different frequencies (i.e., the spectral

emissions mask), there is a spatial specification

as well. The phased array approach provides a

natural solution to these challenges.

As opposed to a fixed directional antenna

system, phased arrays allow the beam to be

steered electronically in different directions,

enabling accurate velocity and location estima-

tion of objects that appear within the narrow

beam. In addition to vehicular radar applica-

tions, such object and motion sensors could

potentially be useful in many other applica-

tions.

Taking advantage of silicon integration, spa-

tial processing, and large available bandwidth

will make

gigabit wireless LAN

and

low-cost versa-

tile vehicular radar

a reality. In this article we dis-

cuss the integration issues for such a

multiple-antenna system in silicon and demon-

strate the first silicon-based fully integrated

phased array receiver at 24 GHz.

HASED

RRAY

: A S

PECIAL

ASE OF

MIMO S

YSTEMS

Antenna arrays can be implemented on either

the transmit side (multiple-input single-output:

MISO), the receive side (single-input multiple-

output: SIMO), or both ends (multiple-input

multiple-output: MIMO).

In MIMO systems, prevalent multipath scat-

tering increases channel capacity by creating

stochastically independent channels between

each of the transmitter and receiver antenna

array elements. For example, if there are

ele-

ments on each of the transmitter and receiver

sides, scattering effectively creates

parallel

channels between the transmitter and the receiv-

er [2, 3]. The theoretically promised linear

increase in capacity is never fully realized in

practice because the effective channels created

are not completely independent. Although the

improvement factor is often less than

, practical

demonstrations of MIMO systems have shown

A. Hajimiri, A. Komijani, A. Natarajan, R. Chunara, and X. Guan, California Institute of Technology

H. Hashemi, University of Southern California

BSTRACT

Phased array systems, a special case of MIMO

systems, take advantage of spatial directivity and

array gain to increase spectral efficiency. Imple-

menting a phased array system at high frequency

in a commercial silicon process technology pre-

sents several challenges. This article focuses on

the architectural and circuit-level trade-offs

involved in the design of the first silicon-based

fully integrated phased array system operating at

24 GHz. The details of some of the important

circuit building blocks are also discussed. The

measured results demonstrate the feasibility of

using integrated phased arrays for wireless com-

munication and vehicular radar applications at

24 GHz.

Phased Array Systems in Silicon

IEEE Communications Magazine • August 2004

123

that substantial increase in channel capacity is

possible (20–40 b/s/Hz for an 8-transmitter 12-

receiver MIMO system [4]). However, the spac-

ing between antennas has proven to be a

practical barrier to the implementation of multi-

ple antenna arrays for mobile applications at fre-

quencies in the low gigahertz range (e.g.,

~ 15

cm @ 2 GHz). The size constraints mandate the

move to higher frequencies.

Phased array, historically employed in radar

and radio astronomy applications, is a class of

multiple antenna systems. It can form beams and

nulls in desired directions by controlling the time

delay and gain of the signal in each path inde-

pendently. The array gain and spatial directivity

achieved in a phased array system provide a log-

arithmic increase in channel capacity with an

increase in the number of elements in the phased

array due to the logarithmic dependence of

channel capacity on signal-to-noise ratio (SNR).

The benefits provided by the beam directionality

of a phased array transmitter, shown in Fig. 1a,

can be likened to the advantages of a narrow

flashlight beam over the omnidirectional incan-

descent bulb. In a flashlight, most of the light

energy is focused only in the desired direction,

as opposed to a bulb’s indiscriminate illumina-

tion in all directions. Thus, to obtain a given

power intensity at the destination, much lower

power needs to be radiated at the source for a

directional beam, as compared to an omnidirec-

tional one. At the same time, less interference is

generated via this collimation of power.

Similarly, in phased array receivers, signals

from multiple antennas are delayed individually

to compensate for the path length difference in

that direction and are then added coherently. As

shown in Fig. 1b, phased array systems are capa-

ble of amplifying signals coming from one direc-

tion while attenuating interfering signals from

other angles.

A phased array increases the effective SNR at

the output of the receiver, thereby improving its

sensitivity. With sufficient antenna spacing, the

black-body radiation noise of each antenna is

uncorrelated to the noise of the other antennas

in the array. Furthermore, the receiver noise

sources in each signal path before power com-

bining are independent. As a result, the time-

delayed signals from the antenna array add in

amplitude (coherently) while the noise adds in

power (incoherently). This results in a 10log

(

)

Figure 1.

(a) A phased array transmitter focuses the beam at a desired angle; b) a phased array receiver

focuses on the desired signal while it attenuates an interferer coming from another direction.

(a)

(b)

Receiver

active beam

Receiver

antenna array

Beam null

Interference

Wave

front

∆

Delay

Transmitter

active beam

Transmitter

antenna array

The array gain and

spatial directivity

achieved in a

phased-array

system provide a

logarithmic increase

in channel capacity

with an increase in

the number of

elements in the

phased-array due to

the logarithmic

dependence of

channel capacity on

signal-to-noise ratio.

IEEE Communications Magazine • August 2004

124

[dB] improvement in the SNR at the output of

the

element phased array receiver.

The improvement in the SNR at the target

phased array receiver and reduction in the level

of interference generated for other users because

of the directionality of a phased array transmit-

ter lead to substantially higher data rates and

frequency reuse ratios, while lowering the power

requirements of the transmitter. Although there

are more active elements in a phased array sys-

tem, its power consumption is still lower than

that of single-path systems for the same data

rate.

ELAYED

RRAY OR

HASED

RRAY

Phased array is perhaps a misnomer for these

systems given that true time delay, and not phase

shift, is required in each path for coherent addi-

tion of signals. As shown in Fig. 1b, when a

plane electromagnetic wave arrives at an anten-

na array at an angle of

with respect to the nor-

mal to the array plane, the signal is received by

each antenna at a different time due to the dif-

ference in propagation path length. In general,

an angle-dependent time delay in each path at

the receiver can compensate for the arrival delay

and effectively “listen” to a desired direction. In

a one-dimensional array, the angle of incidence,

, is related to the delay difference of two adja-

cent elements,

∆

, the spacing of two adjacent

antennas,

, and the speed of light,

, via

.sin(

) =

∆

(1)

The beam forming works independent of the fre-

quency and bandwidth of the signal with ideal

delay elements following each antenna, as shown

in Fig 1b. Unfortunately, there are practical

challenges to implement such broadband delay

elements in the radio frequency (RF) signal

path, such as signal attenuation, noise, and lin-

earity degradation, as well as signal dispersion.

Fortunately, in many practical applications, par-

ticularly in wireless communications, the band-

width of interest is a small fraction of the center

frequency; hence, a uniform delay (linear phase)

is only required over this narrow bandwidth. A

simple way to realize the delay is to approximate

it with a constant phase shift. This aligns the car-

rier phase of different paths. However, the mod-

ulating signal is not delayed appropriately,

leading to some dispersion in the demodulated

signal. A higher modulation-bandwidth-to-carri-

er-frequency ratio results in larger signal disper-

sion, manifested by the spreading of the

constellation points. This distortion results in an

increased bit error rate (BER) in wireless com-

munication systems and in a reduced radial reso-

lution in radar applications.

The effect of using phase shifting instead of

true time delay compensation can be seen in the

simulation results shown in Figs. 2a and 2b.

They show the simulated constellation of the

received signal (without noise) for an eight-ele-

ment phased array receiver at bit rates of 1 Gb/s

and 10 Gb/s at the worst case incident angle of

with respect to normal, using a quaternary

phase shift keying (QPSK) binary-coded complex

modulation scheme with a carrier frequency of

24 GHz. The antenna elements are placed

/2 =

2.5 mm apart in a one-dimensional array of

eight. Receiver noise was not simulated to fully

expose the limitations of the constant phase

approximation. A square-root raised cosine fil-

ter with a rolloff factor,

, of 0.5 is used at both

transmitter and receiver for pulse shaping. A

of 0.5 corresponds to a spectral efficiency of 1.33

b/s/Hz.

As the direction of the beam becomes more

oblique, the delay between the paths increases,

and so does the error introduced by constant

phase shift approximation. The constellation

spreading is a function of the signal’s angle of

incidence, ratio of signal bandwidth to carrier

frequency, and pulse shaping used. Error vector

magnitude (EVM) is a measure of constellation

spreading and is the root mean squared differ-

ence between the perfectly demodulated and

measured signals. The EVM of the received sig-

nal was calculated for different signal band-

widths and angles of incidence, and the results

are plotted in Fig. 2c, assuming continuous

phase control at the local oscillator (LO). As can

be seen, for a carrier of 24 GHz, even for bit

rates as high as 1 Gb/s and an incidence angle of

(worst case), EVM is lower than 2 percent,

so the signal integrity is maintained without

additional equalization. Given the 250 MHz

wireless communication bandwidth, phase shift

of the carrier at 24 GHz (a

center

close to a

factor of 0.01) is a very good approximation for

the delay and sufficient for reliable communica-

tion. However, for broadband communication or

to achieve fine radial resolutions in pulsed

phased array radars, it may be necessary to use a

better approximation of the actual delay rather

than constant phase shift.

A phase shifter implementation in which the

phase can be varied in discrete steps only intro-

duces additional dispersion for certain angles of

incidence, as shown in Fig. 2d. For example, in

the phased array receiver described in this arti-

cle, 16 discrete phases of LO are interpolated to

obtain 32 discrete phases (5-bit resolution) that

are then used to compensate the narrowband

phase shift of the carrier frequency in each path.

This discrete method can only precisely compen-

sate the carrier phase shift at 32 angles of inci-

dence between –90

and +90

. For all other

angles, the signal constellation in each received

path is rotated by an angle equal to the phase

quantization error, which depends on the exact

phase shift necessary in each path for the given

angle of incidence. Since the constellation for

each receiver path is rotated differently, there

will be interference between the in-phase (I) and

quadrature-phase (Q) demodulated channels.

Figure 2d plots the simulated EVM as a func-

tion of the angle of incidence when discrete

phase shifts are used at the receiver for 8, 16,

and 32 available phases, as well as a continuous

version (Fig. 2c). The signal has a bandwidth of

7.5 GHz, and all other simulation parameters

are identical to those used in Figs. 2a and 2b.

Using a 5-bit phase shifting scheme with phase

steps of 5.6

causes a peak EVM of 12 percent

at an incidence angle of 75

, which is only 1.14

times larger than the peak EVM generated if an

Although there are

more active elements

in a phased array

system, its power

consumption is still

lower than that of

single-path systems

for the same data

rate.

IEEE Communications Magazine • August 2004

125

LO with continuous phase shifting were avail-

able. In the latter case, the peak naturally hap-

pens at an incidence angle of 90

, which

corresponds to the largest time delay between

antennas. It is evident from Fig. 2d that a 3-bit

phase shifting resolution results in a much larger

EVM relative to a 5-bit phase resolution. If a 3-

bit phase shifting scheme with 45

phase steps

were used, this peak would occur at an incidence

angle of 60

, with a peak EVM value 180 per-

cent higher than the peak EVM value for a con-

tinuous version. The relative degradation due to

a coarse phase resolution increases for higher

bandwidth-to-carrier ratios.

ILICON

MPLEMENTATION

Advances in silicon process technologies for

integrated circuits have resulted in very fast tran-

sistors with cutoff (unity current gain) frequen-

cies above 100 GHz. However, transistor speed

is only one of the parameters affecting system

operation. Additional constraints imposed by the

low breakdown voltages, losses of integrated pas-

sive elements, low power budget, as well as cost

and area constraints have important bearings on

overall system performance. Therefore, the

architecture of the phased array system has to be

chosen carefully to ensure repeatability and reli-

ability.

Ideally, broadband variable delays are needed

to make the signals from all the paths coherent

before they are combined. Such a variable delay,

if implemented in the signal path at RF, can

reduce power consumption. The gain of the

delay stage should be independent of the delay,

as a change in amplitude with different delays

will lead to distortion when the signals are com-

bined. Thus, the delay element should have large

and accurate variations in delay (0–140 ps @ 24

GHz for an 8-element array, with spacing of

between antennas) and low loss. Such delay ele-

ments are quite challenging to implement.

As mentioned before, for narrowband signals

the delay can be approximated by a phase shift.

Figure 3 shows the different stages at which the

phase shift can be implemented in a simple two-

element phased array receiver example. In the

signal path, the phase shift can be provided at

RF (Fig. 3a), intermediate frequency (IF)/base-

Figure 2.

The simulated constellation for a QPSK modulation scheme at a carrier frequency of 24 GHz for bandwidths of: a) 750

MHz and b) 7.5 GHz; c) EVM for the two constellation in Fig. 1a and b vs. angle of incidence; d) the effect of phase quantizati

on error

for 3-bit, 4-bit, and 5-bit resolution at different beam angles compared to continuous LO phase resolution.

BW = 750 MHz,

= 24 GHz

Data rate = 1 Gb/s

(a)

Incidence angle ( ̊)

(c)

EVM (%)

Incidence angle ( ̊)

(d)

EVM (%)

1 Gb/s

10 Gb/s

BW = 7.5 GHz,

= 24 GHz

Data rate = 10 Gb/s

(b)

Continuous phases

32 phases (with

interpolation

)

16 phases (raw)

8 phases

IEEE Communications Magazine • August 2004

126

band (Fig. 3b), or digitally (Fig. 3c). Equivalent-

ly, the phase shift can also be provided by down-

converting the signal in each path with a phase

shifted LO signal (Fig. 3d). The architecture

selection is accompanied, as always, by certain

trade-offs in power consumption, capacity, sili-

con area, and system reliability.

An architecture with controllable phase

shifters in each RF path and signal combining at

RF has advantages with respect to lower power

consumption as there only needs to be one

IF/baseband stage (Fig. 3a). Additionally, since

all the interferers are nulled out at RF, the lin-

earity requirements of the IF/baseband stage are

reduced. If the signal is delayed by time,

, the

carrier at frequency

undergoes a phase shift

equal to 2

. Since a phase shift of

is equiva-

lent to a phase shift of 2

, the phase shifter

only needs to provide phase shifts between 0 and

. Again, the gain should be constant across

phase shifts, and the phase shifter should have

low loss. There have been some phase shifters

reported at lower frequencies, but their size and

performance do not make them suitable for an

integrated phased array system. The study of

high-frequency phase shifters is an active area of

research [5].

While it is possible to utilize phase shifters in

the IF stage, they increase power consumption

because in an

element receiver, there will have

to be

downconversion mixers before the phase

shifters (Fig. 3b). Since the value and therefore

the size of passive components (i.e., inductors,

capacitors, and transmission lines) needed to

provide phase shift is inversely proportional to

the frequency, implementing the phase shifters

at IF will increase system area.

Another architectural choice is to do away

with analog phase shifting entirely, opting for

baseband digital delay (Fig. 3c). This increases

the flexibility of the system, as it can now be

configured as both a phased array or a MIMO

system depending on the application. However,

this advantage is offset by the high power con-

sumption of such a system, which is essentially

equivalent to

receivers operating in parallel

while sharing no blocks except the frequency

synthesizer. Also, it places tough performance

criteria on the analog-to-digital (A/D) converter

in order to provide accurate delay. Additionally,

as the interferers are still present, the linearity

and dynamic range of the IF stage and A/D con-

verter will also have to be substantially higher,

leading to higher power consumption. As an

illustration, imagine a digital array of eight

receivers where each has an 8-bit A/D converter

that samples the signal with a 100 MHz channel

bandwidth at twice the Nyquist rate. These num-

bers are reasonable for such a system. The base-

band data-rate of the whole system can be

calculated as 76.8 Gb/s. This requires a high-

speed interface, and a power-hungry and expen-

sive signal processing core.

As compared to a signal path implementation

at RF, IF, analog baseband, or digital signal pro-

cessing, a phase shifter in the LO stage is rela-

tively easier to implement (Fig. 3d). Since the

downconversion mixers have their best perfor-

mance when they are hard-driven, the LO stages

should preferably be operated in saturation.

Figure 3.

Different architectures for implementing phase shift: a) RF phase shifting; b) IF phase shifting;

c) digital phase shifting; d) LO path phase shifting.

A/D

(d)

DSP

•

Phase (time) shift

•

Amplitude control

•

Combine

(a)

phase shift

Digital

phase shift

A/D

(c)

(b)

phase shift

LO path

phase shift

As compared to a

signal path

implementation at

RF, IF, analog

baseband, or digital

signal processing, a

phone shifter in the

LO stage is relatively

easier to implement.

IEEE Communications Magazine • August 2004

127

Noting that the output of the VCO has constant

amplitude as well, the amplitude and phase vari-

ations can be completely decoupled. Therefore,

each path will have a constant gain irrespective

of phase shift. Since in this architecture there is

only one IF amplifier followed by two (I and Q)

A/D converters, the power consumption is

reduced from that of an IF phase shift architec-

ture.

A 24 GH

HASED

RRAY

ECEIVER

The trade-offs described above led to an LO-

phase-shifting-based phased array receiver. The

block diagram and circuit schematics of the

eight-element 24 GHz phased array receiver are

shown in Fig. 4. In order to avoid the dc offset

and other problems associated with a homodyne

receiver, a two-stage heterodyne radio architec-

ture was adopted (Fig. 4a). The two LO fre-

quencies were chosen to be 19.2 GHz and 4.8

GHz. With this choice, both LO frequencies can

be generated in one frequency synthesizer phase-

locked loop with the use of a frequency divide-

by-four block.

The phased array receiver has been designed

and fabricated in a IBM 7HP SiGe BiCMOS

process with maximum cutoff frequency,

, of

120 GHz for bipolar devices and minimum chan-

nel length of 0.18

m for complementary metal

oxide semiconductor (CMOS) transistors [6].

The process offers five metal layers. As the top

Figure 4.

a) The block diagram of the eight-path phased array receiver implemented in silicon; b) phase selection circuitry; c) 24 GHz

low noise amplifier; d) RF mixer and combiner; e) multiple-phase LO.

1...8-

(c)

out-

out+

in-

bias

270

247.5

225

67.5

(e)

112.5

135

167.5

22.5

202.5

180

337.5

315

292.5

CNTRL

in+

bias1

bias2

LO+

IF+

IF-

Matched

to LNA

output

(d)

IF+ IF-

Mixer

cell 1

RF1

LO1-

LO1+

bias

out

IF-

IF+

IF1+

IF1-

IF3+

IF3-

IF2+

IF2-

IF5+

IF5-

IF4+

IF4-

IF7+

IF7-

IF8+

IF8-

IF6+

IF6-

(b)

Phase-selector

Sign-selector

67.5

bias

1...8-

sel

1...8+

22.5

112.5

135

157.5

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

LO1

16:1 phase-selector

19.2GHz 16-phase

VCO

Phase frequency

detector

1...

Phase-select

shift-register

Band-gap

and PTAT

references

bit

cntrl

CLK

LO1

LNA RF mixer

24-GHz

4.8-GHz

75-

MHz

mixer

amplifier

LO2_I

LO2_Q

(a)

buffer

ref

supply

LO1

LO2_Q

LO2_I

Loop filter

Charge pump

1...16-

1...16+

1...8+

sel

180

sel

180

..8+

. . .

sel

Mixer

cell 1

RF1

LO1-

LO1+

Mixer

cell 2

RF2

LO2-

LO2+

Mixer

cell 3

RF3

LO3-

LO3+

Mixer

cell 4

RF4

LO4-

LO4+

Mixer

cell 5

RF5

LO5-

LO5+

Mixer

cell 6

RF6

LO6-

LO6+

Mixer

cell 7

RF7

LO7-

LO7+

Mixer

cell 8

RF8

LO8-

LO8+

IEEE Communications Magazine • August 2004

128

two metal layers are thicker, they are used for

on-chip routing of high-frequency signals and

implementing on-chip spiral inductors. The

receiver can be broadly divided into circuits in

the signal path, and circuits for LO generation

and phase selection. It is important to note that

while this architecture is more suitable for beam-

forming, the circuits in themselves are still appli-

cable to a full

-element MIMO receiver.

IGNAL

ATH

Each RF front-end consists of a two-stage low

noise amplifier (LNA) (Fig. 4c) and a Gilbert-

type mixer. The outputs of all eight mixers are

combined in the current domain and terminated

with a tuned load at the IF frequency, as shown

in Fig. 4d. Impedance matching networks were

implemented on-chip between RF stages to max-

imize power transfer. More information on the

design of the front-end can be found in [7]. The

image frequency of the first downconversion is

located at 14.4 GHz. The signals at this frequen-

cy are attenuated by the narrowband transfer

function of the front-end (i.e., antenna and

LNA). The cascaded LNA stages alone provide

around 35 dB of image rejection. Since the trans-

missions around the image frequency band (14.4

GHz) are mainly low-power satellite signals, no

image rejection architecture is used at the RF

stage. The final downconversion to baseband is

done by a pair of quadrature mixers. The divide-

by-four block that is used to generate the second

LO naturally produces in-phase and quadrature-

phase signals to drive these mixers.

LO M

ULTIPLE

HASE

ENERATION

A single oscillator core is used to generate mul-

tiple phases of a single frequency. Multiple phas-

es can be generated by extracting signals from

equidistant nodes of an oscillator loop, as shown

in Fig. 4e. A phase shift of 360

is maintained

across the oscillator feedback loop in order to

maintain stable oscillation. In our design, a ring

comprising 8 fully-differential CMOS amplifiers

forms the 19 GHz VCO capable of generating

16 phases. As the structure is differential, flip-

ping one of the connections halves the number

of amplifying stages in the ring from 16 to 8.

Each amplifier produces a phase shift of 22.5

phase shift at 19 GHz (Fig. 4e). It can be shown

that in order to achieve a 22.5

phase shift, each

amplifier should be tuned close to the oscillation

frequency. Each of the designed amplifier stages

draws less than 3.2 mA from a 2.5 V supply,

resulting in total power consumption of 63 mW

for the oscillator.

HASE

ISTRIBUTION AND

ELECTION

The oscillator core generates 16 discrete phases

that are used to control the phase of each path.

The 16 generated phases of the VCO are fed

into the phase selection circuitry of each path in

a symmetric manner to ensure that the delays of

the traces connecting these blocks are equal for

all the oscillator phases. The phase selectors

(Fig. 4b) can be digitally controlled to interpo-

late between two adjacent phases; thus generat-

ing 32 equally spaced LO phases. However,

there may be amplitude and phase variations in

each path. These variations are because of the

mutual coupling and the small mismatches in

delivering the LO phases to different receiver

paths. For example, based on electromagnetic

simulations, the wavelength of a 19 GHz signal

in a typical microstrip line in the silicon technol-

ogy used is about 6 mm; hence, a length differ-

ence of 40

m corresponds to a phase difference

of 2.5

. The phase and amplitude mismatches

among various paths deteriorate the side lobe

attenuation or equivalently degrade the ability of

the phased array to reject interfering signals.

Figure 5a shows the symmetric tree structure

used to transfer all 16 phases of the LO signals

to the phase selection circuitry of each path with

minimal mismatch between the paths. Figure 5b

shows the ordering of the phases in the LO

phase distribution network. It was determined

that this ordering minimized the coupling

induced mismatch. In order to reduce the loss,

the top two metal layers in the process were

used for distributing multiple LO phases. The

minimum spacing between lines in these thicker

metal layers is around 5

m; therefore, the phase

distribution network occupies a significant frac-

tion of the chip area. The large size of the LO

phase distribution network, and sensitivity to

mismatch and coupling is a disadvantage of this

architecture.

The phase selectors in each path provide the

appropriate phase of the LO to the correspond-

Figure 5.

a) Tree structure for LO phase distribution; b) order of angles in the LO distribution network.

(a)

(b)

1st path

2nd path

3rd path

4th path

5th path

6th path

7th path

8th path

T15

T16

The 16 generated

phases of the VCO

are fed into the

phase selection

circuitry of each

path in a symmetric

manner to ensure

that the delays of

the traces

connecting these

blocks are equal for

all the oscillator

phases.

IEEE Communications Magazine • August 2004

129

ing RF mixer. The phase selectors are equivalent

to analog multiplexers, and the LO phase for

each path is controlled irrespective of the phase

of the other paths. The phase selection data is

serially loaded to an on-chip shift register using

a digital serial interface.

The phase selector in each receiver path has

access to all 16 phases of the LO via the 8 differ-

ential LO outputs. In order to minimize the

phase-selection circuit complexity, the appropri-

ate phase of the local oscillator for each path is

selected in two steps. Initially, an array of 8 dif-

ferential pairs with switchable current sources

and a shared tuned load are used to select one

of the 8 differential outputs of oscillator (Fig.

4b).

This topology accommodates phase interpola-

tion using the appropriate digital control word.

When two (or more) phase branches are select-

ed by turning on the tail current sources associ-

ated with those phases, the current addition at

the output results in interpolation between the

two (or more) selected phases, as shown in Fig.

4b. By interpolating two adjacent phases, 32

equally spaced phases (5-bit resolution) can be

generated.

The next stage consists of two cross-coupled

differential pairs. This stage can provide either a

or 180

phase shift (i.e., the output is either

the input or its inverted version). The two stages

of phase selection result in complete access to

all LO phases. Notably, the two stages are

designed to provide high gain in order to restore

the amplitude of the LO signal that is attenuated

because of the loss of the distribution network

and mismatch between components.

EASURED

ERFORMANCE

The results of the measurements performed on

the receiver have been summarized in Fig. 6a.

The overall noise figure of the system is 7.4 dB

over a bandwidth of 250 MHz. The array func-

tion improves the output signal power by 18 dB

while increasing the noise power only by 9 dB,

resulting in an improvement of 9 dB in the out-

put SNR compared to the SNR at the antenna

for eight elements. Therefore, the SNR at the

baseband is about 1.6 dB

better

than the SNR at

each antenna. Figure 6b shows the measured

beam formed when signals from four paths are

added after phase shifting for three different

angles and compares it to the theoretically calcu-

lated patterns. Due to the inherent agility of the

phase selection blocks, the phase configuration

can be switched at a speed on the order of the

logic switching time. Signal combining in the

current domain results in an increase in the sig-

nal power of 18 dB. Thus. the eight-element

Figure 6.

a) Measured receiver performance summary; b) four-element theoretical and measured array

patterns; and c) die photo of the eight-path fully integrated receiver implemented in silicon.

3.5 mm

3.3 mm

LO phase

distribution

1 RF channel

(LNA and

mixer)

1-channel

phase

selector

Biasing

circuitry

16-phase

oscillator

Frequency

synthesizer

IF mixers and

BB amps

0.8

0.6

0.4

Theoretical

170

160

150

140

130

120

110

100

Peak gain

Noise-figure

Input referred

1 dB comp. point

IIP3

On-chip image

rejection

Input reflection

coefficient (

)

43 dB

Total array gain

61 dB

Technology

IBM 7HP SiGe,

120 GHz HBT

0.18

m CMOS

Die area

3.5 mm

3.3 mm

SNR improvement 9 dB

Beam steering

resolution

< 10

Beamforming

peak-to -null ratio

Up to 20 dB

(four-path)

Power dissipation

@ 2.5 V

287 mA

7.4 dB

–

27 dBm

–

11.5 dBm

35 dB

–

10 to

–

20 dB

Signal path performance (per path)

Synthesizer

locking range

2 GHz (10%)

VCO

2.1 GHz/V @

19.2 GHz

VCO phase-noise

–

103 dBc/Hz @

1 MHz offset

LO path performance

Complete receiver performance

(eight paths)

Implementation

(a)

(b)

(c)

0.8

0.6

0.4

0.2

Measured

170

160

150

140

130

120

110

100

0.8

0.6

0.4

0.2

Measured

170

160

150

140

130

120

110

100

0.8

0.6

0.4

0.2

Measured

170

160

150

140

130

120

110

100

The two stages of

phase selection

result in complete

access to all LO

phases. Notably, the

two stages are

designed to provide

high gain in order

to restore the

amplitude of the

LO signal which is

attenuated because

of the loss of the

distribution network

and mismatch

between

components.

IEEE Communications Magazine • August 2004

130

array exhibits a total gain of 61 dB and has a

beamforming peak-to-null ratio of 20 dB. It

draws a constant 287 mA from a 2.5 V supply,

irrespective of beam direction.

A die micrograph of the fully integrated 24

GHz phased array receiver is shown in Fig. 6c.

The complete receiver occupies 3.3

3.5 mm

silicon area. As mentioned before, the phase dis-

tribution network occupies a significant portion

of the chip area. Except for eight receiver inputs

at 24 GHz, differential in-phase and quadrature-

phase baseband outputs (four pads), and phase

locked loop (PLL) reference (one pad), all the

other pads are either ground or biasing/control

voltage pads, demonstrating a fully integrated

phased array receiver in silicon for the first time.

EFERENCES

[1] FCC 02-04,Sec. 15.515.15.521

[2] I. E. Telatar,

“

Capacity of Multi-Antenna Gaussian Chan-

nels,

”

Bell Labs Tech. Memo.

, June 1995.

[3] G. J. Foschini, Jr. and M. J. Gans,

“

On Limits of Wireless

Communication in a Fading Environment when Using

Multiple Antennas,

”

Wireless Pers. Commun.

, vol. 6,

no. 3, Mar 1998, pp. 311

–

55.

[4] P. W. Wolniansky et al.,

“

V-BLAST: An Architecture for Real-

izing Very High Data Rates over the Rich-Scattering Wire-

less Channel,

”

Proc. URSI ISSSE

, 1998, pp. 295

–

300.

[5] H. Zarei and D.J. Allstot,

“

A Low-Loss Phase Shifter in

180 nm CMOS for Multiple Antenna Receivers,

”

Proc.

ISSCC

, Feb. 2004, pp 392

–

93.

[6] A. Joseph

et al.

“

A 0.18

m BiCMOS Technology Featuring

120/100 GHz (fT/fmax) HBT and ASIC-Compatible CMOS

Using Copper Interconnect,

”

BCTM Proc.

, 2001, pp. 143

–

46.

[7] H. Hashemi, X. Guan, and A. Hajimiri,

“

A Fully Integrat-

ed 24 GHz 8-Path Phased-Array Receiver in Silicon,

”

Proc. ISSCC

, Feb. 2004, pp. 390

–

91.

IOGRAPHIES

AJIMIRI

received a B.S. degree in electronics engineer-

ing from Sharif University of Technology, and M.S. and

Ph.D. degrees in electrical engineering from Stanford Uni-

versity. He has been on the Faculty of Electrical Engineer-

ing at California Institute of Technology (Caltech),

Pasadena, since 1998, where he is an associate professor

of electrical engineering and director of the Microelectron-

ics and Noise Laboratories. His research interests are high-

speed and RF integrated circuits. He is a co-author of

The

Design of Low Noise Oscillators

, and holds several U.S. and

European patents. He is an Associate Editor of

IEEE Journal

of Solid-State Circuits

and a member of the Technical Pro-

gram Committee of the International Solid-State Circuits

Conference (ISSCC). He was the Gold Medal winner of the

National Physics Competition and the Bronze Medal winner

of the 21st International Physics Olympiad, Groningen,

Netherlands. He was a co-recipient of the ISSCC 1998 Jack

Kilby Outstanding Paper Award and a three-time winner of

the IBM faculty partnership award as well as a National

Science Foundation CAREER award.

Abbas Komijani received B.S. and M.S. degrees in electron-

ics engineering from Sharif University of Technology. He is

currently working toward a Ph.D. degree at Caltech. His

research interests include high-frequency power amplifiers,

wireless transceivers, phased array architectures, and delta-

sigma data converters. He was a design engineer with

Emad Semiconductors, where he worked on CMOS chipsets

for voiceband applications from 1997 to 1999. He was a

design engineer with Valence Semiconductors, where he

worked on data converters for VoIP applications from 1999

to 2000.

RUN

ATARAJAN

received a B. Tech degree from the Indian

Institute of Technology, Madras, in electrical engineering

and an M.S. degree from Caltech. He is currently working

toward his Ph.D. at Caltech.. His current research interests

include design of integrated high-frequency circuits, wire-

less transceivers, and modeling of parasitic coupling in

integrated circuits. He received the Analog Devices Out-

standing Student IC Designer Award in 2004.

UMI

HUNARA

received a B.S. degree in electrical engineer-

ing in 2004 from Caltech. She will commence her Master

’

and Ph.D. studies in September 2004 at the Massachusetts

Institute of Technology in electrical engineering, and health

sciences and technology. Her research interests include

low-power integrated devices for communication as well as

nano- and micro-scale sensing and other biological applica-

tions.

IANG

UAN

received a B. S. degree in electrical engineering

from Tsinghua University and an M. Eng. degree in electri-

cal engineering from the National University of Singapore.

He is currently working toward a Ph.D. degree at Caltech.

From 1996 to 1997 he was a research assistant at the Inte-

grated Circuits Group, Instituto Superior Tecnico, Lisbon,

Portugal, involved in the development of a data acquisition

chip for electrocardiogram remote monitoring devices. In

summer 2003 he was a co-op researcher at the IBM

Thomas J. Watson Research Center, Yorktown Heights,

New York.

OSSEIN

ASHEMI

received B.S. and M.S. degrees in electron-

ics engineering from Sharif University of Technology. He

received a second M.S. and a Ph.D. in electrical engineering

from Caltech. He joined the Department of Electrical Engi-

neering

—

Electrophysics at the University of Southern Cali-

fornia in 2003 as an assistant professor, where the core of

his research constitutes the study of the fundamentals of

high-speed and RF communication circuits and systems,

along with integrated implementations. He has been a

recipient of the Outstanding Accomplishment Award from

the von Brimer foundation in 2000, Outstanding Student

Designer Award from Analog Devices in 2001, and an Intel

fellowship in 2002. He is an Associate Editor of

IEEE Trans-

actions on Circuits and Systems, Part II

The signal combining

in the current

domain results in an

increase in the signal

power of 18 dB.

Thus, the eight-

element array

exhibits a total gain

of 61 dB and has a

beam forming peak-

to-null ratio of 20

dB. It draws a con-

stant 287 mA from

a 2.5 V supply,

irrespective of the

beam direction.