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Published 1998 | public
Book Section - Chapter

A Low-Power Wide-Dynamic-Range Analog VLSI Cochlea


In this paper we describe a cochlea that attains a dynamic range of 6ldB at the BF of a typical cochlear stage by using four techniques: 1. The previously described WLR 2. A low-noise second-order filter topology 3. Dynamic gain control (AGC) 4. The architecture of overlapping cochlear cascades In addition, we use three techniques that ensure the presence of a robust infrastructure in the cochlea: l. Automatic offset-compensation circuitry in each cochlear filter prevents offset accumulation along the cochlea. 2. Cascode circuitry in the WLRs increase the latter's DC gain, and prevent low-frequency signal attenuation in the cochlea. 3. Translinear bipolar biasing circuits provide Qs that are approximately invariant with corner frequency, and allow better matching. Bipolar biasing circuits were first used in cochlear designs by [32]. We shall discuss all of these preceding techniques in this paper.

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© 1998 Kluwer Academic

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March 5, 2024