S-1
Supporting Information
Silicon Heterojunction Microcells
Maggie M. Potter
1,
⟙
, Megan E. Phelan
2,
⟙
, Pradeep Balaji
3
, Phillip Jahelka
2
, Haley C. Bauser
2
,
Rebecca D. Glaudell
4
, Cora M. Went
4
, Michael J. Enright
5
, David R. Needell
2
, André Augusto
3
,
Harry A. Atwater
2, *
, Ralph G. Nuzzo
5, 6, *
⟙
Authors contributed equally to the work
*
haa@caltech.edu, r-nuzzo@illinois.edu
1. Department of Chemical and Biomolecular Engineering, University of Illinois at Urbana
Champaign, Urbana IL 61801, USA
2. Department of Applied Physics and Materials Science, California Institute of
Technology, Pasadena CA 91125, USA
3. Solar Power Laboratory, Arizona State University, Tempe AZ 85287, USA
4. Department of Physics, California Institute of Technology, Pasadena, CA 91125
5. Department of Chemistry, University of Illinois at Urbana Champaign, Urbana IL 61801,
USA
6. Surface and Corrosion Science, School of Engineering Sciences in Chemistry,
Biotechnology and Health, KTH Royal Institute of Technology, Stockholm 114 28,
Sweden
S-2
Silicon Heterojunction μ-cell Device Fabrication
Overview: Si Microcell Fabrication Techniques
SHJ solar microcells were fabricated from non-metallized macro-scale 6 in × 6 in SHJ
devices from Arizona State University (ASU). The 6 in × 6 in SHJ devices [(100) orientation]
were fractured along the <110> planes into smaller devices sized ca. 1.5 in × 1.5 in for
subsequent processing.
For DRIE-processed samples, an initial patterning step via standard micron-scale
photolithography, followed by 6:1 buffered oxide etching (BOE) of the SiNx protective
coating, defines the outline of the microcell device array (
Figure 1a,b
). The pattern
includes 15 μm bars to anchor the microcells to the source substrate, as shown by the red
arrow in the confocal image in
Figure 1a
. The bulk substrate is (100) orientation, and the
microcell array pattern is aligned such that the <110> planes accord with the lateral
dimensions of the devices. The underlying ITO layer is then etched with fresh 9 M hydrogen
chloride (HCl) at room temperature.
1
The lateral dimensions of the microcells are then
defined via DRIE
2-4
by etching completely through the substrate using the Bosch process
with thick (10 μm) photoresist as the masking layer. After DRIE, residual photoresist can be
removed using either an O
2
-plasma treatment or Radio Corporation of America (RCA)-1
treatment. Damaged Si is removed from the device edges by etching for 13 minutes in a 3 M
KOH/2 M IPA solution in deionized water at 60°C.
5
RCA-1 and RCA-2 cleaning processes
are then employed again to clean any residual organic and metallic sidewall contamination,
respectively. Finally, the SiNx protective coating is removed through a 6:1 BOE dip,
resulting in a suspended microcell array (
Figure 1c
). A subset of the suspended microcell
array, featuring a device with removed sidewall damage, is shown in the scanning electron
microscope (SEM) images in
Figure 1f,g
.
For the laser cutting process, after the SiNx protective coating is deposited on the
front and back of the devices, the samples are sent for commercial laser cutting (Micron
Laser Technology) with an overlay analogous to the DRIE-processed materials. With the
laser cutting process, we find that material removed from the laser cut substrate trenches
is re-deposited along the top perimeter of the substrate as a powder (
Figure S2
), as shown
in the confocal image in
Figure 1d
and represented by the rendered red line in
Figure 1e
.
S-3
In a manner similar to the DRIE-based processing, the powder, as well as the damaged Si on
the device edges, is removed by etching for up to 16 minutes in a 3 M KOH/2 M IPA
solution in de-ionized water at 60°C. We again employ an RCA-1 and RCA-2 cleaning
process. The SiNx protective coating is then removed through a 6:1 BOE dip, yielding the
final suspended microcell wafer array (
Figure 1c
). The powder is largely removed by the
KOH etching process; the resulting cell surface and angled sidewall profile is shown in the
SEM images in (
Figure 1h-i,
cf.
Figure S2
). In the case of both the DRIE and laser cutting
processing methods, a contact grid was excluded, as we determined the required grid
finger spacing was larger than the devices themselves, given their small size.
We note that a 45% wt. KOH solution at 60°C was also explored for damage removal
for both DRIE and laser cutting dicing processes, with less favorable outcomes. The
conditions here, in which the <110> crystal planes etch at a local maximum rate,
5
proved to
be less effective at producing a smooth, damage-free sidewall morphology than the 3 M
KOH/2 M IPA solution. Additionally, such high KOH concentrations result in damage to the
SiNx protective layer on the top of the devices, which in turn led to damage to the top
surface ITO layer due to unintentional etching during both the 45% wt. KOH and RCA-2
processing steps that reduced both the device J
sc
and efficiency.
Overview: Microcell Sidewall Morphology
Both presented micro-fabrication techniques yield (from a geometric perspective) high
quality diced microcell arrays, at the target lateral dimensions, that are suspended on the
sample wafer via their 15 μm anchor bars, as shown in
Figure S3a
. This design enables a
microcell array patterned sample that yields ca. 700 microcells (for the 400 μm × 400 μm
device size). To qualitatively compare how each fabrication technique affects the microcell
performance along the dicing line, we examine the microcell edges using SEM. A rendered
image of the region of interest—the microcell edge—is shown in
Figure S3b.
Representative SEM images of the microcell edges are shown directly following dicing (i.e.,
as-cut) in
Figure S3c,d
for DRIE and laser cut microcells, respectively. The horizontal
scallops along the microcell sidewall are a byproduct of the DRIE Bosch process (
Figure
S3c
), which cycles between etching and deposition of a fluorocarbon to achieve a highly
vertical etch profile. The effects of trench width on sidewall morphology during DRIE
S-4
etching are shown in
Figure S4a
. We observe characteristic horizontal Bosch scallops
along the sidewalls within the wider trenches of the pattern and vertical striations within
the narrower trenches.
6
In contrast, laser cut processing results in a nonuniform sidewall
morphology (
Figure S3d
) due to recast material and physical/thermal damages (i.e., heat
affected zone) resulting from the laser cutting process.
6
Sidewall images following damage removal (3 M KOH/2 M IPA and RCA processes,
as described in Methods) are shown in
Figure S3e,f
for the DRIE and laser cut microcells,
respectively. As shown, the damage removal processes result in considerably smoother
sidewall
morphologies
for
both
dicing
techniques,
in
comparison
to
the
morphologies/textures seen in the as-cut SEM images. Damage removal on DRIE-processed
microcells enables smoother sidewalls, on average, than damage removal on laser cut
microcells (
Figure S3b
), due to the alignment of the vertical profiles of each with the
<110> planes of the device substrate, which etch at a local minimum rate compared to
other processing-developed features in the 3 M KOH/2 M IPA wet etchant solution.
5
After
laser cutting, the microcell sidewalls are tapered outward slightly, and the initial recast Si
material does not uniformly correspond to any particular crystal plane, and is likely to be
amorphous. Even so, the damage removal process successfully reveals the <110> plane in
most areas along the device sidewalls, as shown in the SEM image.
Sidewall morphologies tend to vary after the 3 M KOH/2 M IPA damage removal
process for both the DRIE and laser cutting process, as shown in
Figure S5.
In the case of
DRIE, we have noted pinned etchant features that arise as a consequence of reaction
product (H
2
) bubbles forming and either attaching to or passing by the device sidewalls.
7-8
Similar effects have also been noted related to etchant inhomogeneities and product
removal in ways most deeply impacting the laser cut devices.
8
The current etchants and
methods do not temper this impact from moass and heat transfer, which will require a
more robust mitigation strategy in a more fully optimized process design to reduce
variations in sidewall morphology (e.g., implementation of a flow reactor for damage
removal).
Overview: Passivation
To apply passivation coatings to the microcell edges, the substrate is first submerged in 6:1
S-5
BOE for 6 s to remove the native oxide layer
9
from the device edges, as shown in
Figure S1
,
and then either PECVD or ALD processing of the aforementioned coatings is performed to
achieve the desired passivation. For the a-Si:H passivation, a-Si:H
10-12
followed by SiNx are
deposited conformally via PECVD. As shown in the SEM image in
Figure 4a
, the PECVD
process allows for coating of the microcell edges with a total a-Si/SiNx thickness of 80 nm,
with reflection high-energy electron diffraction measurements (RHEED) confirming the
amorphous nature of the a-Si material. TiO
2
coatings are deposited via ALD, at a deposition
thickness of 1.5 nm. For dicing, we implement a modified lower-throughput DRIE method
(0.25 μm/cycle vs. 3.2 μm/cycle) that generates less initial sidewall damage (
Figure S7b,
cf.
Figure S3c
), but limits sample accessibility as a consequence of the slow processing
rate. Damage removal (
Figure S7b
, 6 min in 3 M KOH/2 M IPA) results in a flat, smooth
surface for minimized recombination at the edge surfaces, as well as ease of application
and efficacy
13
of surface passivation along the edges using a variety of deposition
techniques with varying degrees of conformality.
Processing Details: SiNx Deposition
The samples were initially coated with 360 nm of SiNx via plasma-enhanced chemical
vapor deposition (PECVD) (Oxford Instruments, Plasmalab System 100) on the front and
back as a protective and adhesion layer. The deposition was done at a pressure of
1800 mTorr, an RF power of 90 W with a pulse time of 12 s, an LF power of 90 W with a
pulse time of 8 s, a temperature of 200°C, a 5% SiH
4
in Ar flow rate of 500 sccm, a NH
3
flow
rate of 30 sccm, and an N
2
flow rate of 1300 sccm. A deposition time of 4 minutes resulted
in a SiNx
layer thickness of 360 nm, as measured by ellipsometry (J.A. Woolam Company,
M-2000 with CompleteEASE control and analysis software).
Processing Details: Laser Cutting
After deposition of the protective SiNx coating, samples were sent to Micron Laser
Technology (Hillsboro, Oregon) for cutting in the microcell array pattern at a cutting
velocity of 1.3 mm/s, according to proprietary cutting parameters.
Processing Details: SiNx and ITO Etching for DRIE
S-6
The microcell array was patterned onto the SiNx with alignment to the <110> planes using
standard photolithography (AZ 9260, AZ Electronic Materials, 10 μm Thick):
─
Dehydration bake on hotplate at 110°C for 5 minutes
─
HMDS vapor treatment at room temperature for 5 minutes
─
Spin-coat AZ 9260 at 2400 rpm for 60 seconds
─
Softbake at 110°C for 2 minutes and 45 seconds
─
Expose to 1500 mJ/cm
2
at 405 nm (Suss MicroTec, MA6 and MA6/BA6)
─
Develop in AZ 400K 1:4 (1 part developer, 4 parts water) for 4 minutes
─
O
2
plasma treatment for 3 minutes (ca. 250 mTorr, 150 W, 6 sccm O
2
) (PIE Scientific,
Tergeo Plus)
The microcell array pattern was etched into the SiNx by submersion in buffered oxide
etchant (BOE) 6:1 solution (Sigma-Aldrich or Transene) for ca. 90 s. Then, the μ-cell array
pattern was etched into the ITO by submersion in a fresh 9 M HCl (J.T.Baker, Hydrochloric
Acid, 36.5–38%) solution for 5–6 minutes.
Processing Details: ITO Etching and DRIE of Si
Subsequently, the photoresist was removed from the back side of the wafer only using
acetone, and the Si was etched all the way through using deep reactive ion etching (DRIE)
(Oxford Instruments, Plasmalab System 100). For the “fast” rate DRIE etching, the sample
was adhered directly to a 6-inch–diameter sapphire carrier wafer using Fomblin oil prior
to etching. The etch cycle was 17 s long with an SF
6
flow rate of 160 sccm, a valve position
set to 31.5° (80 mTorr – 90 mTorr), a coil power of 2500 W, and a platen power of 100 W.
The deposition cycle was 11 s long and used a C
4
F
8
flow rate of 90 sccm, a pressure of
30 mTorr, a coil power of 2150 W, and a platen power of 10 W. The etch temperature was
-5°C, and 18–30 cycles etched through 80 μm of Si (etch rate roughly 3.2 μm/cycle). For the
“slow” rate DRIE etching, the sample was adhered directly to a 6-inch-diameter silicon
carrier wafer using Fomblin oil prior to etching. The etch cycle was 10 s with an SF
6
flow
rate of 150 sccm, a pressure of 30 mTorr, a coil power of 1500 W, and a platen power of
40 W. The deposition cycle was 7 s long and used a C
4
F
8
flow rate of 110 sccm, a pressure of
30 mTorr, a coil power of 1500 W, and a platen power of 10 W. The etch temperature was
S-7
-5°C, and ca. 340 cycles etched through 80 μm of Si (etch rate roughly 0.25 μm/cycle). After
completion of the DRIE etch, the carrier wafer + sample was rinsed in acetone and IPA to
release the sample from the carrier wafer. Residual photoresist and Fomblin oil were
removed from the sample by O
2
plasma cleaning (Plasma-Therm, SLR 720) on both sides of
the sample for 15–20 minutes at room temperature and 20 mTorr, with an O
2
flow rate of
20 sccm, and a power of 80 W.
Processing Details: Damage Removal and Cleaning
After both DRIE and micro-laser cutting, sidewall damage was removed by first dipping in
BOE 6:1 for 6 s to remove the native oxide from the devices sidewalls, followed by etching
in 3 M KOH/2 M IPA (Macron Fine Chemicals, Potassium Hydroxide, Pellets) (Sigma
Aldrich, 2-Propanol) solution in DI water at 60°C or 45 wt.% KOH (Sigma Aldrich) (at 60°C.
The samples were then cleaned using standard RCA cleaning procedures as shown below:
─
RCA-1 Clean:
Etch in RCA-1 solution (H
2
O:NH
3
:H
2
O
2
= 5:1:1) at 70°C–80°C for 10 min
─
RCA-2 Clean:
Etch in RCA-2 solution (H
2
O:HCl:H
2
O
2
= 5:1:1) at 70°C–80°C for 10 min
Native oxide on the sidewalls was removed by a dip in BOE 6:1 for 6 s in before and after
each cleaning step. After cleaning, the SiNx protective layer was removed from the
front/back of samples by submersion in BOE 6:1 for 50 s–90 s. The “slow” rate DRIE
samples were cleaned in RCA-1 only, and lacked a SiNx protective/adhesion layer due to
poor selectivity inherent to DRIE etching recipe.
Processing Details: Passivation
Lifetime measurements on (110) Si test wafers, with naturally grown native oxide on a
clean and damage-free surface, reveal an SRV of 708 cm/s for native oxide passivation.
Prior to additional passivation, the sample was submerged in BOE 6:1 for 6 s to remove the
native oxide from the device sidewalls. The sample was then immediately transferred to
the atomic layer deposition (ALD) or PECVD chamber (Ultratech, Simply ALD, Fiji G2)
(Oxford Instruments, Plasmalab System 100) for deposition of passivation coatings.
Deposition parameters for each film type were as follows:
S-8
─
PECVD a-Si, recipe 1:
temperature of 200°C, pressure of 800 mTorr, power of 10 W
(30.3 mW/cm
2
), 5% SiH
4
in Ar of 250 sccm, deposition time of 4 minutes.
─
PECVD a-Si, recipe 2:
temperature of 200°C, pressure of 400 mTorr, power of 10 W
(30.3 mW/cm2), 5% SiH4 in Ar of 250 sccm, deposition time of 8 minutes.
─
PECVD SiNx:
temperature of 200°C, pressure of 1800 mTorr, an RF power of 90 W
with a pulse time of 12 s, an LF power of 90 W with a pulse time of 8 s, a 5% SiH
4
in
Ar flow rate of 500 sccm, a NH
3
flow rate of 30 sccm, and an N
2
flow rate of
1300 sccm.
─
ALD TiO
2
:
temperature of 80°C, TTiP precursor with H
2
O pulses, 104 total cycles for
1.5 nm total deposition (90 cycles for 1.3 nm, 69 cycles for 1 nm, and 49 cycles for
0.7 nm).
To remove PECVD films selectively from the top of the devices after passivation, a thick Si
carrier wafer was first treated according to the following using standard photolithography
(AZ 9260, AZ Electronic Materials, 10 μm Thick):
─
Dehydration bake on hotplate at 110°C for 5 minutes
─
HMDS vapor treatment at room temperature for 5 minutes
─
Spin-coat AZ 9260 at 2400 rpm for 60 s
The samples with the devices suspended in the microcell array were then gently placed on
top of the thick photoresist-coated carrier wafer, and the device-carrier assembly was
softbaked at 110°C for an additional 2 minutes and 45 seconds. Then, the device-carrier
assembly was re-patterned with photoresist (AZ 9260, AZ Electronic Materials, 10 μm
Thick) (recipe as previously described) with alignment to previous patterning for the
purpose of covering the device edges. The films on the top of the devices were then
removed by inductively coupled plasma
‑
reactive ion etching (ICP-RIE) (Oxford
Instruments, Plasmalab System 100) using the following etching parameters: T = 20°C, C
4
F
8
= 45 sccm, O
2
= 2 sccm, P = 7 mTorr, ICP generator power (AKA coil power) = 2100 W, RF
power (AKA platen power) = 200 W.
Printing and Testing
S-9
To test the devices, the anchor bars were broken to release each device from the array
using either a syringe needle or an appropriately-sized PDMS stamp. The devices were then
placed atop a Cr/Au (10 nm/300 nm) interconnection deposited by e-beam (Kurt J. Lesker
Company, Labline) on a transparent, double-sided, ITO-compatible tape from 3M (25 μm
thick, 3M OCA 8146-1) on a standard glass substrate. To measure JV characteristics
repetitively on small microcells under the same illumination conditions, we aimed to
consistently probe specifically the corner of each device to minimize losses associated with
shadowing from the probe.
Modelling
We develop a device physics model of the SHJ microcells using Synopsys’ Sentaurus to
understand how device geometry and quality of edge passivation influences SHJ microcell
performance metrics. In particular, we model square-shaped microcell devices with
varying lateral dimensions (200 μm × 200 μm to 1000 μm × 1000 μm) and thicknesses (10
μm to 150 μm). A schematic of the SHJ microcell device architecture is shown in
Figure 1a
.
As shown in
Figure S6a
, the square-shaped devices are modeled as 3D cylinders, to save
considerable time from a computational standpoint, by construction of 2D rectangular half-
devices and then assuming cylindrical symmetry about the y-axis (including the exposed
area after breaking the anchor bars, as shown in red). Current-density-voltage (JV)
characteristic curves and performance parameters are simulated for AM1.5G direct
illumination conditions.
As shown in
Figure 1a
, the SHJ wafer base in the device physics simulations consists
of n-type crystalline-Si, varying from 10 μm to 150 μm in thickness (shown here at 80 μm
thickness). The top and bottom surfaces of the base are passivated with thin (10 nm)
intrinsic (i-type) hydrogenated amorphous silicon (a-Si:H), assuming a surface
recombination velocity (SRV) indicative of high-quality surface passivation (SRV = 2
cm/s).
14-16
The emitter and field passivation are composed of p-type a-Si:H (10 nm) and n-
type a-Si:H (10 nm), respectively. ITO is included on the top and bottom of the structure to
serve as both an anti-reflective coating and contact material to combat the low lateral
conductivity of the a-Si:H.
17
To circumvent the need to model carrier transport through
S-10
ITO, we define the contacts as the entire interface between the amorphous-Si (a-Si) and ITO
layers on the top and bottom in the Sentaurus model. As shown on the edges of the device
architecture in
Figure 1a
, a passivation coating with a defined edge recombination velocity
(ERV) at the passivation-coating/base interface is added to the microcell sidewalls to
model the influence of recombination along the device edges on SHJ microcell performance
parameters.
Solar μ-cell Characterization and Testing
RHEED
Reflection high-energy electron diffraction (RHEED) images were acquired with a STAIB
Instruments RHEED 30 at 20 kV voltage and 1.5 A filament current. With the electron beam
at a low incidence angle, the diffraction pattern depends on the crystal structure of the
surface layers. When the beam is incident on an amorphous surface, no coherent diffraction
occurs, and the electrons reach the detector in an incoherent cloud, as seen in Figure 6.
[Single crystal surfaces appear as vertically oriented streaks, corresponding to the Ewald
sphere that defines the coherent diffraction condition intersecting with the surface layer
reciprocal lattice rods. Such defined streaks are clearly absent on the samples, confirming
an amorphous structure.]
Suns-Voc
Suns-Voc (Sinton Instruments) measurements were taken on both bulk (unpatterned) SHJ
wafers and SHJ microcells to measure the PV cell IV curve without the effects of series
resistance. These measurements enabled comparison of microcell performance to that of
the bulk unprocessed wafer.
Light JV
Current-Voltage measurements were taken under a calibrated AM1.5G (1000 W/m
2
) solar
simulator (ABET 2000, 1000W) using a voltage sweep of -0.5 V to 0.8 V, compliance = 1 mA.
S-11
Photocurrent Mapping
Light Beam Induced Current (LBIC) images were taken by raster scanning a 633 nm laser
across the region of interest. The process was done using a confocal microscope (Zeiss Axio
LSM 710) at 5× magnification.
Imaging
Confocal images were taken using a Zeiss Axio LSM 710 at magnifications ranging from 5×–
20×. Scanning electron microscope (SEM) images were obtained using either of the
following manufacturers/models: FEI (now ThermoFisher), Quanta 200F or FEI (now
ThermoFisher), Nova 200 NanoLab.
Lifetime
To test the surface recombination velocity (SRV) of each passivation coating, we deposited
each passivation material on the front and back of high-lifetime <110> wafers (Siltronix,
(110) ± 0.5°). We then measured the lifetime of the passivated surface using a Lifetime Tool
(Freiberg Instruments, MDPspot). SRV was then calculated using the following formula,
where W = 450 μm:
1
휏
푒푓푓
=
1
휏
푏푢푙푘
+
2
∗
푆푅푉
푊
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