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Published October 2010 | Supplemental Material
Journal Article Open

Reduction of thermal conductivity in phononic nanomesh structures


Controlling the thermal conductivity of a material independently of its electrical conductivity continues to be a goal for researchers working on thermoelectric materials for use in energy applications and in the cooling of integrated circuits. In principle, the thermal conductivity κ and the electrical conductivity σ may be independently optimized in semiconducting nanostructures because different length scales are associated with phonons (which carry heat) and electric charges (which carry current). Phonons are scattered at surfaces and interfaces, so κ generally decreases as the surface-to-volume ratio increases. In contrast, σ is less sensitive to a decrease in nanostructure size, although at sufficiently small sizes it will degrade through the scattering of charge carriers at interfaces. Here, we demonstrate an approach to independently controlling κ based on altering the phonon band structure of a semiconductor thin film through the formation of a phononic nanomesh film. These films are patterned with periodic spacings that are comparable to, or shorter than, the phonon mean free path. The nanomesh structure exhibits a substantially lower thermal conductivity than an equivalently prepared array of silicon nanowires, even though this array has a significantly higher surface-to-volume ratio. Bulk-like electrical conductivity is preserved. We suggest that this development is a step towards a coherent mechanism for lowering thermal conductivity.

Additional Information

© 2010 Macmillan Publishers Limited. Received 30 April 2010. Accepted 21 June 2010. Published online 25 July 2010. This work was funded by the Department of Energy (Basic Energy Sciences). The authors acknowledge the Intel Foundation for a graduate fellowship (J.-K.Y.), KAUST for a Scholar Award (D.T.), and the National Science Foundation for a graduate fellowship (J.V.). The authors also thank J. Tahir-Kheli for helpful discussions and A. Boukai for early assistance with device fabrication. J.-K.Y. thanks H. Do (UCLA Nanoelectronics Research Facility) for helpful suggestions regarding device fabrication. Author contributions: J.-K.Y., S.M. and J.R.H. conceived the work and wrote the manuscript. J.-K.Y. and S.M. developed the fabrication protocols and carried out fabrication of the devices, transport measurements and data analysis. S.M., J.-K.Y. and J.R.H. interpreted the experimental findings. D.T. and J.-K.Y. devised the experimental set-up, and D.T. wrote the data acquisition, analysis and error propagation routines. J.V. helped with device fabrication. J.V., D.T. and J.-K.Y. wrote the Supplementary Information.

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Supplemental Material - nnano.2010.149-s1.pdf


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August 19, 2023
October 20, 2023