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Published September 2015 | metadata_only
Book Section - Chapter

A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS


This paper describes an ultra-low-power VCSEL transmitter in 32nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. The resulting nonlinearity and loss in bandwidth is modelled and compensated by a nonlinear equalization technique. The time domain optical responses for "one" and "zero" bits are used to find the optimum equalization technique. The rising and falling edges were equalized separately and the equalization delay is selected based on the bias current of the VCSEL. The transmitter achieves energy efficiency of 0.77pJ/b at 20Gb/s.

Additional Information

© 2015 IEEE. The authors thank D. K. Serkland and Sandia National Labs for providing the VCSELs and helping with the measurement setup, and DARPA LEAP for chip fabrication.

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August 22, 2023
August 22, 2023