Phase Noise and Fundamental Sensitivity of Oscillator-Based Reactance Sensors
This paper investigates the fundamental sensitivity of oscillator-based reactance sensors, which are widely used in numerous types of biomedical sensing applications. We first show that the intrinsic sensitivity is limited by the 1/ƒ^3 phase noise of the sensing oscillators. To achieve sensor detection sensitivity below this limit, a correlated double counting (CDC) noise suppression scheme is proposed to cancel the correlated 1/ƒ^3 phase noise in differential frequency detections. The suppression effect of the CDC scheme is thoroughly modeled. Moreover, the CDC scheme is extended to a high-order configuration, called the Interleaving-N CDC, to further improve the frequency resolution. In addition, we show that the weighting sequence on the Interleaving-N CDC data can be optimized as a digital noise filter to maximize the noise suppression. Given a sensing oscillator with any phase-noise profile, a general weighting optimization method is proposed based on the minimum variance distortion less response. As an example, an oscillator-based inductive magnetic sensor array in a 45-nm CMOS silicon-on-insulator process is implemented with the proposed CDC scheme. It achieves a noise suppression of 10.4 dB with basic CDC sheme and a frequency resolution of 0.128 parts per million for Interleaving-N CDC scheme, both with negligible power overhead. This enables inductance-change detection sensitivity of 0.41 fH for a low-Q on-chip 1.6-nH inductor with a quality factor of only 4.95.
© 2013 IEEE. Manuscript received October 15, 2012; revised March 12, 2013; accepted March 14, 2013. Date of publication April 17, 2013; date of current version May 02, 2013. This work was supported by the California Institute of Technology under a Caltech Innovation Initiative (CI2) Research Grant. The authors would like to thank C. Sideris, California Institute of Technology, Pasadena, CA, USA, for his help on developing the CMOS magnetic sensor. The authors also would like to acknowledge Prof. P. P. Vaidyanathan, California Institute of Technology, Dr. S. Kousai, Toshiba, and the members of the Caltech High-Speed Integrated Circuit group (CHIC) for technical discussions.