Supporting Information
“Nanofabricated Neural Probes for Dense 3-D Recordings of
Brain Activity”
Gustavo Rios,
1,
∗
Evgueniy V. Lubenov,
1,
∗
Derrick Chi,
3
Michael L. Roukes,
1, 2, 3, 4,
†
and Athanassios G. Siapas
1, 2,
‡
(California Institute of Technology, Pasadena, CA 91125, USA)
1
Division of Biology and Biological Engineering
2
Division of Engineering and Applied Science
3
Division of Physics, Mathematics, and Astronomy
4
Kavli Nanoscience Institute
(Dated: September 9, 2016)
∗
These authors contributed equally to this work.
†
Electronic address:
roukes@caltech.edu
‡
Electronic address:
thanos@caltech.edu
1
Neural Probe Fabrication
Neural probes were fabricated on 200 mm (8 in) SOI wafers. The fabrication protocol
consists of
∼
56 processing steps requiring the use of 7 stepper field masks (field size: 22
mm
×
22 mm) and both LETI’s CMOS and MEMS foundries. Neural probe material
composition is summarized in Table S1. Key steps used in the fabrication of the neural
probes are given as follows and depicted in Figure S1:
1
2
3
4
5
6
7
8
9
10
11
Silicon
Thermal Oxide
Buried Oxide (BOx)
Gold (Seed: Ti and Ni)
Parylene HT
PECVD SiN
Copper (Barrier: TiN)
PECVD Oxide
FIG. S1:
Neural probe fabrication steps. (1)
Substrate used: 200 mm SOI wafer.
(2)
Bottom
insulator growth.
(3)
Copper interconnects.
(4)
Top insulator deposition.
(5)
Via etching and
copper fill.
(6)
Gold microelectrode and output pad electroplating.
(7)
Top side device definition
and etch.
(8)
Parylene HT deposition and etch.
(9)
Back side thermal oxide etch.
(10)
Handle
layer etch.
(11)
Final device release. Color legend defines the materials used in the process. See
text for details.
Bottom insulator (1-2)
(1) Alignment marks are patterned and etched on the SOI wafer
(device layer: 17
μ
m, BOx: 1
μ
m, handle layer: 700
μ
m). (2) Thermal oxide is
grown. It serves as the bottom insulator for the nanoscale interconnects and as a
crucial stress compensation layer. Its thickness is determined by design, as opposed to
process requirements, as is the case with subsequent dielectric layers. FEM simulations
2
TABLE S1:
Neural probe layers and materials.
Layer
Material
Thickness
Substrate
Si / BOx
17
μ
m / 900 nm
Bottom Insulator
SiO
2
0.8, 1.2, 1.5
μ
m
Metal Interconnects
Cu
300 nm
Top Insulator
SiO / SiN
500 nm / 40 nm
Metal Electrodes and Pads
Au
300 nm
Biocompatible Layer
Parylene HT
1.5
μ
m
determined that a thickness of 1.2
μ
m was adequate for proper stress compensation,
while devices with three different SiO
2
thicknesses (0.8, 1.2, 1.5
μ
m) were fabricated.
Metal interconnects (3)
The wafer is transferred into the CMOS foundry for this step.
A dielectric layer stack of SiO / SiN (300 nm / 40 nm, SiN serves as an etch stop) is
deposited using PECVD and the interconnect metal lines are patterned using a 248 nm
deep ultra violet (DUV) stepper. Trenches are etched (RIE) into the dielectric stack
and copper is electroplated using the CMOS industry standard damascene process
(width = 300 nm, AR = 1, TiN 20 nm as barrier layer).
Top insulator (4-5)
(4) A second dielectric layer stack of SiO / SiN (500 nm / 40 nm) is
deposited (PECVD) on top of the copper interconnects and serves as a top insulator.
SiN is used solely as an etch stop. (5) Vias are etched (RIE) through the top insu-
lator layer at the recording electrode and interface pad locations. A second copper
damascene process fills the vias. This is the last processing step in the CMOS foundry.
Metal electrodes and interface pads (6)
The wafer is transferred into the MEMS
foundry for the remaining procedures. Gold is electroplated (300 nm Au; 100 nm
Ti and 350 nm Ni used as seed layers) and etched to define the recording electrodes
and interface pads.
Top side device definition (7)
Top side device definition is performed by etching
through the multiple dielectric layers (RIE), the silicon device layer (DRIE) and 90%
of the BOx layer (RIE, 900 nm).
3
Biocompatibility layer (8)
Parylene HT (1.5
μ
m) is deposited (CVD, Specialty Coating
Systems) onto the primed wafer (Silane, A174). Depositing Parylene HT after top side
definition assures that the top and side walls of the shanks are fully coated. Following
deposition, Parylene HT is protected with photoresist optimized for step coverage and
the recording sites are patterned. Finally, Parylene HT is etched (RIE) to expose the
gold recording sites.
Back side device definition (9-11)
(9) The back side thermal oxide layer is patterned
and etched (RIE) exposing the silicon device layer. (10,11) Final DRIE etch is per-
formed to completely etch away the silicon from the device layer (700
μ
m). The
left-over BOX layer (100 nm) serves as an etch stop and guarantees a smooth back-
side surface required for subsequent packaging steps. Finally, the thin BOX layer is
etched (RIE), fully releasing the nanoprobes. Anchors keep the nanoprobes in place
on the wafer until they are manually extracted.
Data Acquisition Architecture
Each module of the data acquisition (DAQ) system is designed to support 256 channels,
i.e. the number of recording electrodes on a nanoprobe. Just as the nanoprobes are stacked
to build a 3-D recording array, the DAQ modules are stacked to scale up the back-end data
acquisition system. Figure S2 shows 4 modules assembled into a 1024-channel system. The
raw analog signals from the recording electrodes feed into a custom headstage. The head-
stage provides signal conditioning, multiplexing, and digitization of the analog nanoprobe
signals from within the implant package. Two versions of these boards were designed and
built. The acute version, depicted in the block diagram, has eight 32-channel Intan chips
(RHD2132), while the chronic version contains four 64-channel Intan bare dies (RHD2164).
At the headstage signals are filtered (0.1 Hz–7.5 kHz passband), amplified in 2 stages (Gain
= 192 V/V = 45.6 dB), multiplexed (256:8), digitized (16-bit), and transmitted out (SPI
bus) through a custom cable. Custom SPI cable adapter reroutes the lines to allow interfac-
ing directly to Intan’s back-end hardware platform using its commercial SPI cables. From
there signals enter an USB/FPGA interface module (Opal Kelly XEM6010). The FPGA in
this module (Xilinx Spartan-6 XC6SLX150-2) is programmed to control the behavior of the
headstage over SPI and to provide both data and command interface to the host computer
4
host
computer
acquire
process
store
control
AC-couple
bandpass
46dB
gain
256
Signals
signal conditioning PCB with 8 ICs
FPGA
FIFO
CLK
SPI
USB
12.8
MB/s
32:1
MUX
16-bit
ADC
sync
256
Signals
signal conditioning PCB
FPGA
USB
256
Signals
signal conditioning PCB
FPGA
USB
256
Signals
signal conditioning PCB
FPGA
FIFO
CLK
SPI
USB
sync
sync
FIG. S2:
Data acquisition system block diagram.
The 1024-channel system is a stack of
4 identical 256-channel modules. Each module consists of the following components: custom
headstage (signal conditioning PCB), custom 14’ SPI cable tether, custom SPI cable adapter PCB,
4 Intan SPI cables, Intan evaluation board with XEM6010 FPGA Opal Kelly daughter board, USB
cable. The signal path through the system is illustrated in the top headstage. Analog signals are
represented by solid lines and digital signals by interrupted lines. Synchronizing pulses exchanged
between the FPGA boards accomplish coordinated acquisition between the modules.
over USB 2.0 (Rhythm API). Using this platform, 256 channels can be simultaneously ac-
quired and streamed from the headstage at sample rates up to 30 kSamples/s per channel.
Since each group of 32 channels is handled in parallel through a dedicated analog multiplexer
(MUX) and analog-to-digital converter (ADC), the sampling period is time divided into
∼
32
conversion intervals and 8 signals are simultaneously digitized during each interval. For ex-
ample, the 33.33
μ
s sampling period, corresponding to 30 kSamples/s channel sampling rate,
is associated with
∼
1
μ
s sampling delay between adjacent channels, i.e. the MUX switching
rate and ADC conversion rate is
∼
1 MHz. Intan’s RHD2000 interface software and Open
Ephys, both open source, were modified for compatibility with the custom headstages and
enabled real-time data viewing, acquisition, and storage at the host computer. Coordinated
acquisition across multiple 256-channel modules was accomplished by extending the FPGA
and host computer components of the Rhythm API to support a synchronization barrier
during each sample period.
5
Heat Dissipation Analysis
a
Q
max
R
flex
T
intan
T
brain
0
0.5
1
1.5
2
35
37
40
45
One shank
Four shanks
Length of flexible cable, L
flex
[mm]
T
intan
Intan Temperature, T
intan
[°C]
b
FIG. S3:
Thermal insulation by flexible cable. (a)
Simple 1-D model of heat transfer between
an active headstage and a passive nanoprobe implanted in the brain represented as an equivalent
circuit.
̇
Q
max
is the maximum admissible rate of heat transfer into the brain per shank,
T
intan
is the measured steady-state temperature at the Intan signal processing IC on the headstage,
T
brain
= 37
◦
C is the temperature of the brain during normal physiological conditions and
R
flex
is
the thermal resistance of the flexible cable.
(b)
Plot relating the length
L
flex
of the flexible cable to
the temperature at the headstage, assuming a maximum admissible heat flux of 0.4 mW/mm
2
at
the surface of one shank (solid line) and 4 shanks (interrupted line). The red dashed line indicates
the temperature measured at the Intan IC.
Prolonged temperature increase in the brain as little as 0
.
5
◦
C can alter the excitability of
cells, while an increase above 2
◦
C can have severe effects on tissue function [S1]. Therefore
the heat dissipated from all active electronics, i.e. Intan ICs on the headstage, needs to be
directed away from the brain. A basic guideline for implantable devices is that the heat
flux through surfaces in contact with tissue should not exceed 40 mW/cm
2
(0.4 mW/mm
2
)
[S2, S3]. While no specific guideline has been established for brain tissue, the corresponding
limit is likely lower than the figure above. Since a shank that is 5 mm long, 50
μ
m wide, and
20
μ
m thick has a surface area of
∼
0.7 mm
2
, the maximum admissible rate of heat transfer
per shank is
̇
Q
max
= 0
.
28 mW.
To obtain a rough estimate of the heat flow between the active headstage and the ani-
mal’s brain through the flexible cable we used a simple 1-D equivalent circuit model obeying
6
Fourier’s law of thermal conduction (Fig. S3a), where the rate of heat transfer
̇
Q
is propor-
tional to the temperature difference between the headstage
T
intan
and the brain
T
brain
̇
Q
=
T
intan
−
T
brain
R
flex
The coefficient of proportionality is given by the reciprocal of the thermal resistance of the
flexible cable
R
flex
, which is dominated by the gold lines and can be expressed as
R
flex
=
L
flex
k
Au
A
Au
where
L
flex
is the length of the flexible cable in mm,
A
Au
= 256 (lines)
×
5
μ
m (width)
×
0
.
3
μ
m (height) = 3
.
84
×
10
−
4
mm
2
, and
k
Au
= 314 mW
·
mm
−
1
·
K
−
1
is the thermal conduc-
tivity of gold.
How hot can the headstage get before the rate of heat transfer to the brain exceeds
the admissible limit? Letting
̇
Q
=
̇
Q
max
and
T
brain
= 37
◦
C in the equations above and
rearranging gives
T
intan
=
T
brain
+
̇
Q
max
k
Au
A
Au
L
flex
= 37 + 2
.
32
×
L
flex
The above relationship is plotted in Figure S3b for a single shank device (solid line) and for
a four shank device (interrupted line), where the slope is four times steeper.
How hot does the headstage actually get? The total power dissipation of a 32-channel
Intan IC (RHD2132) acquiring wideband (0.1 Hz–10 kHz) signals at peak sampling rate (30
kSamples/s per channel) is 37.3 mW. The temperature of the headstage is dominated by
convective cooling and when a single acute PCB is exposed to the ambient air at 25
◦
C,
Newton’s law of cooling yields
T
intan
= 36
.
9
◦
C, given 298.4 mW of total power dissipation
by 8 ICs, 2
.
4
×
10
3
mm
2
of PCB area, and a convective heat transfer coefficient for air of
10.45 W
·
m
−
2
·
K
−
1
. However, when 4 PCBs are closely stacked together to support a 3-D
array, the headstage temperature increases, since the PCBs sandwiched in the middle do
not effectively exchange heat with the ambient air. A rough upper bound on the PCB
temperature reached under these conditions can be obtained by assuming that 4 times the
power is dissipated by the surface area of a single PCB. Newton’s law of cooling then yields
T
intan
= 72
.
5
◦
C, which would require flex cable length of
∼
16 mm to limit the rate of heat
transfer to the brain below the admissible guideline. Given the design choice of 20 mm cable
length, headstage temperatures up to 83
◦
C can be tolerated.
7
In the above computations the acute headstage is exposed to the ambient air, but in
chronic experiments the headstage is sometimes enclosed in an implant package, thereby
limiting heat exchange with the air. We therefore kept a single headstage running inside
a closed styrofoam cup and using the Intan chip’s internal temperature sensors measured
a steady state temperature of
∼
40
◦
C, which would require
∼
1.5 mm of cable length for
proper thermal insulation. As in the case above, stacking 4 headstages for a chronic 3-D
array would require an order of magnitude longer cables.
In summary, providing a high thermal resistance barrier is essential for limiting the rate of
heat transfer to the brain below the guideline for implantable devices. In our modular design,
the flexible cable fulfills this role. The magnitude of the thermal resistance is proportional
to the flex cable length and the design choice of 20 mm offers appropriate thermal barrier
for both stacked PCBs supporting 3-D arrays and chronic packaging.
Surgical Procedures and
In Vivo
Recording Methods
Male mice (C57BL/6-E; Strain Code 475; Charles River Laboratories),
∼
3 months old,
were anesthetized with 1% isoflurane and surgically implanted under aseptic conditions with
a light-weight, stainless steel ring embedded in dental cement, which allowed for mechanically
stable head-fixation in the recording apparatus, as previously described [S4]. A stainless
steel wire was implanted over the right cerebellum and was used as reference. The skull
was leveled and the locations of the exposure (a rectangle spanning 2 mm to 2.8 mm lateral
and
−
2 mm to
−
3 mm posterior from Bregma) were marked on the skull over the left
hemisphere. Following surgery, mice were returned to their home cage, maintained on a 12
hour light/dark cycle, and given access to food and water
ad libitum
. Mice were given at
least 48 hours to recover before the day of the experiment.
On the day of the experiment mice were anesthetized with 1% isoflurane, head-fixed
in the stereotaxic apparatus (Kopf stereotaxic alignment system), and the skull and dura
over the designated coordinates were removed. After recovery the mouse was head-fixed
on a spherical treadmill within a virtual reality system sitting on an air table (Fig. S4).
Motion of the spherical treadmill drove a virtual reality engine that enabled the mouse
to navigate a virtual linear track for water reward. The nanoprobe array was attached
to a precision manipulator (Luigs & Neumann Junior 4RE 4-axis manipulator) and was
8