22.2
An Octave-Range Watt-Level Fully Integrated
CMOS Switching Power Mixer Array for
Linearization and Back-Off
Efficiency Improvement
Shouhei Kousai
*1*2
and Ali Hajimiri
*1
*1
California Institute of Technology
*2
Toshiba Corporation
© 2009
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International
Solid-State
Circuits
Conference
© 2009
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Outline
• Background
• Power mixer array
• Power mixer details
• Block diagram and operation modes
• Measurement results
•Conclusion
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Solid-State
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Primary Constraints in Wireless Communication
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Pros and Cons of Conventional Approaches
• Class-AB
– Poor efficiency
• Doherty & Out-phasing
– Phase shifter
• Supply modulation
– DC-DC converter
• Digital PA
– Aliasing & output noise
0
1
0.5
Supply modulation
Doherty
Out-phasing
Class-AB
Output Power
Efficiency
Digital PA
© 2009
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Solid-State
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Outline
• Background
• Power mixer array
• Power mixer details
• Block diagram and operation mode
• Measurement results
•Conclusion
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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Envelope (BB)
t
Phase (LO)
t
RF Output
t
t
Power Mixer Array Transmitter Subsystem
• Power generation is done by several identical mixers
• Power mixer array subsumes some of the functionality of
a conventional transmitter
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1
2
3
n
Segmented Power Generation
• When a symbol does not require full output power some
power generation blocks are turned off
Ι
Q
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Back-Off Efficiency Improvement
• Power efficient and compatible with CMOS processes
• CMOS is good at switching on and off
Output Power
Power Consumption
1
2
3
n
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Linearity Improvement
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1
2
3
n
V
k
V
V
1
V
2
V
Linearity Improvement
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Linearity Improvement
• Linearity improves as the output increases
© 2009
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Analog residue of
the BB envelope
Filtered Digital BB Pulse
BB
Envelope
Phase (LO)
t
RF Output
t
BB Input Signal Generation
• Input signals are pulse shaped to avoid spurious and
alias problems
© 2009
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Solid-State
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BB Circuit Sharing
• BB circuits such as DAC and LPF can be shared by
using switch
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Output Network and Signal Combination
• Transformer is suitable for a large impedance
transformation ratio
• Output current of the power mixers can be linearly
combined at the output network
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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Outline
• Background
• Power mixer array
• Power mixer details
• Block diagram and operation mode
• Measurement results
•Conclusion
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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Power Mixer
• Current commuting mixer
• Switching operation
– High Efficiency
– Low Noise
• Amplitude modulation
– “Linear” Amplitude
modulation
– Large bandwidth
• Boost the voltage swing
& output impedance
© 2009
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Solid-State
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Transient Waveform of Power Mixer
• Peak efficiency = 60%, Peak power = 33dBm @ 1.8 GHz
-2
0
2
4
6
8
0
0.2
0.4
0.6
0.8
1
1.2
time [ns]
[V, A]
© 2009
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Solid-State
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© 2009
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Gain and Non-Linearity of Power Mixer
• The transconductance
and
the
current gain
is non-linear to the
differential mode of the input
voltage (
V
DIFF
)
i
RF
i
LO
i
LO,S
1
i
LO
V
DIFF
V
DIFF
© 2009
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International
Solid-State
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1. Class-AB Operation
• These non-linearities can cancel
each other
• Improved back-off efficiency
i
RF
i
LO
i
LO,S
1
i
LO
V
DIFF
V
DIFF
V
CM
© 2009
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Solid-State
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2. Baseband Replica Linearizer
• Dynamically match the power mixer core and BB replica
amplifier using feedback
LO+
LO
-
i
RF+
+
+
LBB+
LBB-
BB
in
-
BB
in
+
BB
out
+
BB
out
-
R
1
R
2
R
1
R
2
BB
out
-B
B
out
+
i
LO+
I
DC
X
Y
Power Mixer Core
Analog BB Replica Linearizer
BB
Replica
R
CM
R
CM
+
+
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
10
M
11
CM-
CM+
i
LO-
i
RF-
CM
Baseband Replica
Amplifier
V
ref
LBB+
LBB-
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
IEEE
Outline
• Background
• Power mixer array
• Power mixer details
• Block diagram and operation modes
• Measurement results
•Conclusion
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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Block Diagram of the Implemented System
Digital
Controller
LBB+
LBB-
CM
LO
-
LO+
On-Chip
I
out
+
I
out
PAD
R
Load
Envelope (BB)
6
6
t
t
Phase (LO)
Bypass
6
6
PM
0
PM
13
PM
14
PM
15
V
DD
C
1
C
2
RF Output
+
LBB+
LBB-
Analog
BB
Distributor
Analog
BB
Replica
Linearizer
Array
BB
in
+BB
in
-
t
Digital LO Distributor
1 : 2
66
CM
6
Digital Control
© 2009
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Solid-State
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1. Baseline Analog (BA) Mode
• Class-AB operation for linearity and efficiency improvement
• Equivalent to one large power mixer
Power Mixer
Array Current
Output Amplitude
(RF)
Input Amplitude
(BB Envelope)
Input Amplitude
(BB Envelope)
Digital
Controller
LO
-
LO+
I
out
+
I
out
Envelope
(BB)
Phase (LO)
PM
0
PM
13
PM
14
PM
15
+
BB
in
+
BB
in
Digital LO Distributor
© 2009
IEEE
International
Solid-State
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© 2009
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2. Linearized Analog (LA) Mode
• One large power mixer with feedback linearizer
Power Mixer
Array Current
Input Amplitude
(BB Envelope)
Output Amplitude
(RF)
Input Amplitude
(BB Envelope)
LO
-
LO+
© 2009
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International
Solid-State
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3. Efficient Segmented (ES) Mode
• Segmented power generation for linearity and efficiency
improvement
Power Mixer
Array Current
Output Amplitude
(RF)
Input Amplitude
(BB Envelope)
Input Amplitude
(BB Envelope)
LO
-
LO+
© 2009
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International
Solid-State
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Die Photo
Analog BB Replica
Linearizer Array
Analog BB
Distributor
• Fully-integrated in a 130nm CMOS Technology
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
IEEE
Outline
• Background
• Power mixer array
• Power mixer details
• Block diagram and operation modes
• Measurement results
•Conclusion
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
IEEE
Frequency Response
28
29
30
31
32
33
11
.5 22
.5
Frequency [GHz]
Output power [dBm]
0
10
20
30
40
50
PAE [%]
Output power
PAE
• PAE is larger than 40% from 1.5 to 2 GHz
• Output power is larger than 1W from 1.2 to 2.4 GHz
LO input power = +3 dBm
BB input(0-p, single) = 450mV
43%
+31.4 dBm
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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Gain and PAE for Different Operation Mode
Frequency = 1.8 GHz, CW
• BA and LA mode have very high linearity
• ES mode and BA mode show improved efficiency
-4
-3
-2
-1
0
1
2
3
-10
0
10
20
30
40
Output Power [dBm ]
Conversion Gain
(Normarized) [dB]
Reference
BA Mode
LA Mode
ES Mode
0
10
20
30
40
50
-10
0
10
20
30
40
Output Power [dBm]
PAE [%]
BA Mode
LA Mode
ES Mode
© 2009
IEEE
International
Solid-State
Circuits
Conference
© 2009
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