Improved Parylene-Packaged Pentacene Thin-Film Transistors
This paper presents improved parylene-packaged thin-film transistors. Several spin-cast dielectrics were investigated to improve the surface roughness of parylene. The corresponding mobility and performance of pentacene thin film transistors were also reported. The relation between pentacene grain sizes and roughness of surfaces where pentacene grows were also investigated. To further improve the mobility, micromachined shadow masks made of silicon and parylene were employed to define the source and drain contacts. The improved pentacene thin-film transistor has a mobility of 0.2 cm^2/V-s and an on/off ratio of 10^4.
Additional Information© 2008 ECS - The Electrochemical Society. The authors would like to thank Mr. Trevor Roper for his assistance with equipment and fabrication. We would also thank Tanya Owen, Christine Matsuki, Agnes Tong and other members of the Caltech Micromachining Laboratory for their assistance.
Published - ECS_Trans.-2008-Lo-51-7.pdf