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Published May 2015 | metadata_only
Book Section - Chapter

DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS


This paper describes DD1, an asynchronous radiation-hard 8-bit AVR^® microcontroller (MCU) implemented in TSMC 40LP, a low-power bulk 40nm CMOS process. Designed for extreme reliability, DD1 uses quasi-delay-insensitive (QDI) asynchronous logic and contains full-custom radiation-hard memories and logic cells. The chip was found fully functional on first silicon over a range of operating voltages from near-threshold (500mV) to above the nominal V_(DD) (1.1V). It qualifies as both ultra-low power (<;100μW/MHz) and radiation-hard by design. At 550mV the MCU operates at 1MIPS with a power consumption of 18μW/MIPS. At 1.1V it runs at 20MIPS consuming 75μW/MIPS (1.5mW total). After extensive testing, it was found to be total-dose and latch-up immune and has an upset immunity of 2E-6 SEE/device-day (CREME96 geosynchronous near-earth orbit).

Additional Information

© 2015 IEEE. Date Added to IEEE Xplore: 09 July 2015. We are grateful to James Lyke and Millay Morgan of AFRL for their support through an SBIR Phase I/II grant from the Air Force Research Laboratories, and David Alexander and Alonzo Vera for their help with the radiation tests. The research described in this paper is in part supported by a grant from the National Science Foundation.

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August 20, 2023
August 20, 2023