of 3
Wafer-bonded single-crystal silicon slot waveguides and ring resonators
Ryan M. Briggs,
a

Michael Shearn, Axel Scherer, and Harry A. Atwater
Thomas J. Watson Laboratory of Applied Physics, California Institute of Technology, Pasadena,
California 91125, USA

Received 9 October 2008; accepted 21 December 2008; published online 13 January 2009

We fabricated horizontal Si slot waveguides with a 25 nm SiO
2
slot layer by bonding thin
Si-on-insulator wafers. After removing the Si substrate and buried oxide from one side of the
bonded structure, grating-coupled waveguides and ring resonators were partially etched into the
Si
/
SiO
2
/
Si device layers. The gratings exhibit efficiencies of up to 23% at 1550 nm and the ring
resonators were measured to have loaded quality factors near 42 000 for the lowest-order
transverse-electric mode, corresponding to a propagation loss of 15 dB/cm. The leaky lowest-order
transverse-magnetic mode was also observed with a propagation loss of 44 dB/cm. ©
2009
American Institute of Physics
.

DOI:
10.1063/1.3070541

Over the last few years, Si photonics technology has
made possible the dense integration of passive waveguides
and resonators. Research in Si photonics is now addressing
the challenge of realizing chip-scale Si-based active devices.
In particular, the concept of generating and amplifying light
at telecommunications frequencies on a Si chip has been of
great interest. One promising approach is to integrate active
gain materials directly into a Si waveguiding layer. Using a
slot waveguide with a Si/slot/Si structure, one can take ad-
vantage of symmetry to maximize overlap of guided modes
with an active slot material and potentially employ the Si
layers for electrical injection. In addition, for transverse-
magnetic

TM

polarized modes, the electric field is en-
hanced in the slot by a factor of
n
Si
2
/
n
slot
2
, making low-index
slot materials advantageous for high modal confinement.
1
Thus, with an active slot layer, and in particular one based on
a low-index matrix such as rare earth doped glass, Si-based
slot structures that exhibit gain and even lasing may be
possible.
2
,
3
While vertical slot waveguides in Si-on-insulator

SOI

have been demonstrated,
4
,
5
it is difficult to fill the high-
aspect ratio slot using conventional thin-film deposition pro-
cesses. Thus, we believe that fabricating structures in a hori-
zontal configuration is more adaptable to applications where
a deposited active slot material is to be used. In this paper,
we present a technique for fabricating Si-based horizontal
slot waveguides that is compatible with deposited active ma-
terials but does not require subsequent deposition of lossy
amorphous or polycrystalline Si layers. Our process uses
room-temperature covalent wafer bonding to transfer the Si
device layer of a SOI wafer onto a second SOI wafer with a
thin SiO
2
slot layer in between, as shown in Fig.
1
. The
resulting layered structure has single-crystalline Si layers
both above and below the slot. Although the devices pre-
sented here are passive, an active silica-based slot layer
could be deposited prior to bonding in order to fabricate a
variety of active devices.
To fabricate our wafer-bonded slot waveguides, we be-
gan with commercially available SOI wafers from SOITEC
with a 3

m buried oxide layer and a 250 nm thick, lightly
doped

10
15
cm
−3

,
p
-type Si device layer that was thinned
to approximately 140 nm using wet thermal oxidation and
buffered hydrofluoric acid

HF

etching. The wafers have a
manufacturer-specified 3

thickness variation of 20 nm for
the Si device layer; however, we measured variations of less
than 5 nm over relevant device areas. A thin thermal oxide
bonding layer was grown using dry oxidation. Cleaved
pieces of the wafers were then prepared and bonded using a
process from Tong
et al.
6
Specifically, the pieces were
cleaned in a modified RCA solution of 1:0.2:5
H
2
O
2
:NH
4
OH:H
2
O, rinsed in de-ionized water, and dipped
in 1:200 HF:H
2
O for 10 s. The samples were then baked at
250 °C, cleaned again in the RCA solution, and treated in an
O
2
plasma at 400 W with an O
2
pressure of 115 mTorr. After
being placed in contact and left at room temperature for at
least 24 h, the samples were annealed at 1100 °C in N
2
.
The Si substrate on one side of the bonded structure was
removed using a combination of mechanical lapping and
a

Author to whom correspondence should be addressed. Electronic mail:
rbriggs@caltech.edu.
FIG. 1.

Color online

a

Cross-sectional TEM micrographs of the fabri-
cated structure, showing all layers

inset

and a higher magnification image
of the bonded slot region.

b

A schematic of the fabrication process flow.
APPLIED PHYSICS LETTERS
94
, 021106

2009

0003-6951/2009/94

2

/021106/3/$23.00
© 2009 American Institute of Physics
94
, 021106-1
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