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Published 1985 | public
Book Section - Chapter

A New Discipline for CMOS Design: an Architecture for Sound Synthesis


A number of logic forms and clocking schemes for cMOS integrated circuits are in common use. The most common logic form consists of two networks of transistors, the gates of which are connected to the input variables. An n-channel network defines the boolean condition under which the output is connected to ground (logic zero). A p-channel network defines the complementary condition under which the output is connected to a logical one. Since in many cMOS processes the output of a single pass transistor cannot be guaranteed to exceed the logic threshold of a typical inverter, pass transistor networks are either forbidden or a complementary transmission gate employing both p and n-channel devices is used. Clocking schemes for cMOS presently offer tradeoffs over a wide range in the risk vs efficiency space. In one scheme, a single phase clock and its complement are distributed, and used to control either transmission gates or transistors controlling power to the p and n-channel switching networks. Proper operation in either case requires that the logic delay of the stage exceeds the skew between the two clock lines. In a much safer approach, a two-phase clock is used, both the clock and its complement being distributed for each phase. In this case risk is eliminated at the expense of doubling the clock wiring. Yet another form is popular in gate-level designs. A single clock is distributed, and locally inverted at masterslave storage elements. Risk in this case is eliminated at the expense of a minimum storage element employing ten or more transistors. In this paper we describe a logic form that retains much of the simplicity, elegance, and compactness of the familiar 2-phase nMOS form, with the added advantage of fully static operation. Formal semantics for circuits implemented in this form are easily derived without detailed circuit or switch-level simulation.

Additional Information

© 1985 Computer Science Press. The authors wish to thank Peter Denyer (University of Edinburgh) for many interesting discussions concerning cMOS design methodology. Jim Campbell (Caltech) has helped in circuit layouts and testing of the IPE chips. Dick Lyon (Schlumberger Research Lab), has provided countless ideas. Special thanks are due Telle Whitney (Caltech) for her critiques and many discussions. This work was supported by the System Development Foundation.

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August 19, 2023
March 5, 2024