CaltechAUTHORS
  A Caltech Library Service

Browse by Eprint ID

Up a level
Export as [feed] Atom [feed] RSS 1.0 [feed] RSS 2.0
Number of items: 1.

DeHon, André and Rubin, Raphael (2004) Design of FPGA interconnect for multilevel metallization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12 (10). pp. 1038-1050. ISSN 1063-8210. http://resolver.caltech.edu/CaltechAUTHORS:DEHieeetvlsis04a

This list was generated on Tue Oct 17 22:41:40 2017 PDT.