Phase and amplitude pre-emphasis techniques for low-power serial links
A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s.
© Copyright 2006 IEEE. Reprinted with permission. Manuscript received October 19, 2005; revised February 16, 2006. [Posted online: 2006-05-30] This work was supported by the Maryland Procurement Office under Contract H98230-04-C-0920 and the National Science Foundation. The authors appreciate discussions with Drs. A. Rylyakov, S. Rylov, J. Bulzachelli, S. Gowda, M. Soyuer, and M. Oprysko regarding the direction and implementation of this project.