A Complementary Pair of Four-Terminal Silicon Synapses

Abstract

We have developed a complementary pair of pFET and nFET floating-gate silicon MOS transistors for analog learning applications. The memory storage is nonvolatile; hot-electron injection and electron tunneling permit bidirectional memory updates. Because these updates depend on both the stored memory value and the transistor terminal voltages, the synapses can implement a learning function. We have derived a memory-update rule for both devices, and have shown that the synapse learning follows a simple power law. Unlike conventional EEPROMs, the synapses allow simultaneous memory reading and writing. Synapse transistor arrays can therefore compute both the array output, and local memory updates, in parallel. We have fabricated prototype synaptic arrays; because the tunneling and injection processes are exponential in the transistor terminal voltages, the write and erase isolation between array synapses is better than 0.01%. The synapses are small, and typically are operated at subthreshold current levels; they will permit the development of dense, low-power silicon learning systems.

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