Instantaneous Clockless Data Recovery and Demultiplexing
An alternative architecture for instantaneous data recovery for burst-mode communication is introduced. The architecture can perform 1:n demultiplexing without additional clock recovery phase-locked loop or sampling blocks. A finite-state machine (FSM) is formed with combinational logic and analog LC transmission line delay cells in a feedback loop. The FSM responds to input data transitions instantaneously and sets the outputs. The system reduces unit interval jitter by a factor of n. The new architecture is demonstrated via a SiGe 1:2 clockless demultiplexer circuit that operates at 7.5 Gb/s.
"©2005 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE." Manuscript received June 4, 2004. This paper was recommended by Associate Editor A. G. Andreou. The authors thank J. Buckwalter for his feedback on the manuscript, H. Hashemi and A. Komijani for their contributions to the layout, and S. Mandegaran for helping with Fig. 4(b).