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Published 1983 | public
Book Section - Chapter

Pooh: A Uniform Representation For Circuit Level Designs


This paper describes a simple but general, technology independent representation for VLSI circuits which maintains connectivity, circuit schematic, and mask geometry information. A transistor level cell is represented as the interconnection of devices along with their types, sizes and placement, and the cell's typed ports. Connection is represented explicitly by shared connection points. A file of technology dependent information indicates how to implement each transistor type, interconnect type and connection point type, as well as how structure types may interact.

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© 1983 IFIP.

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August 19, 2023
March 5, 2024