Minimum Propagation Delays in VLSI

Abstract

With feature sizes decreasing and chip area increasing it becomes more and more time consuming to transport signals over long distances across the chip [5]. Designers are already introducing more levels of metal connections, using wider and thicker paths for longer distances. Another recent development is the introduction of an additional level of connections between the chip and the pc-board, multilayer ceramic chip carriers. The trend is undoubtedly towards even more connecting levels. In this paper we demonstrate that it is possible to achieve propagation delays that are logarithmic in the lengths of the wires, provided the connection pattern is designed to meet rather strong constraints. These constraints are, in effect, satisfied only by connection patterns that exhibit a hierarchical structure. We also show that, even at the ultimate physical limits of the technology, the propagation for reasonably sized VLSI chips is dominated by these considerations, rather than by the speed of light.

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