Published May 1995 | Version Published
Book Section - Chapter Open

Single transistor learning synapse with long term storage

  • 1. ROR icon California Institute of Technology

Abstract

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and floating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the floating gate is decreased by hot electron injection with high selectivity for a particular synapse. The charge on the floating gate is increased by electron tunneling, which results in high selectivity between rows, but much lower selectivity between columns along a row. When the steady state source current is used as the representation of the weight value, both the incrementing and decrementing functions are proportional to a power of the source current.

Additional Information

© 1995 IEEE. The work was supported by the Office of Naval Research, the Advanced Research Project Agency, and the Beckman Foundation.

Attached Files

Published - 00523729.pdf

Files

00523729.pdf

Files (388.5 kB)

Name Size Download all
md5:545b738f8def181355a5551775b876aa
388.5 kB Preview Download

Additional details

Identifiers

Eprint ID
53630
Resolver ID
CaltechAUTHORS:20150113-122333554

Funding

Office of Naval Research (ONR)
Advanced Research Projects Agency (ARPA)
Arnold and Mabel Beckman Foundation

Dates

Created
2015-01-13
Created from EPrint's datestamp field
Updated
2021-11-10
Created from EPrint's last_modified field