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Published August 2015 | public
Journal Article

An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation


This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for fine-tuning. Similar to multiplying delay-locked loops (MDLLs), this architecture limits jitter accumulation to one reference cycle, as jitter during one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase interpolation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8-9.5 GHz, LC VCO's range of operation. First-order dynamic of the acquisition has been analyzed and demonstrated through measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rms jitter of 680 fs. Different components of jitter have been analyzed and separate measurements have been done to support the analysis. The reference spurs are measured to be -64.3 dB below the carrier frequency. At 8 GHz the system consumes 2.49 mW from a 1 V supply.

Additional Information

© 2015 IEEE. Manuscript received December 11, 2014; revised February 07, 2015; accepted April 13, 2015. Date of publication May 13, 2015; date of current version July 24, 2015. This paper was approved by Guest Editor Elad Alon. The authors would like to thank STMicroelectronics for chip fabrication and members of MICS and CHIC lab, particularly B. Abiri, for insightful discussions.

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