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Published June 2006 | public
Journal Article Open

Asynchronous techniques for system-on-chip design


SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed.

Additional Information

© Copyright 2006 IEEE. Reprinted with permission. Manuscript received September 14, 2005; revised March 3, 2006. [Posted online: 2006-07-10] This work was supported in part by the Defense Advanced Research Projects Agency (DARPA). The authors would like to thank J. Dama, W. Jang, M. Josephs, J.L. Martin, M. Naderi, K. Papadantonakis, and P. Prakash for their excellent comments on the paper.


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